On 1/12/2022 06:21, Miroslav Bendík wrote:
> IIRC tests done by Miroslav showed that interrupt 7 was used for
> completing SMBus Block transfers and alike, but not for HostNotify. He
> suspects this is wired via GPIO somehow.
This is just speculation. It may be routed to GPIO pin, but think it's more
likely that AMD implements host notify. I have looked at windwos drivers
and
there is only SMBus driver bundled with synaptics.
Lets look at
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.intel.com%2FAssets%2FPDF%2Fdatasheet%2F290562.pdf&data=04%7C01%7Cmario.limonciello%40amd.com%7Cb813c9d7934b4bb971dc08d9d5c610a4%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637775869527091018%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C2000&sdata=GyQUs1tNgpQDcE%2FeoV1lF%2BKQgFZs3YDgYrP8Z5oCS2E%3D&reserved=0
(PIIX4 from
Intel). There is SMBSLVCNT register (page 152). Last bit (Slave Enable)
should
enable interrupt on host notify if slave address matches content of
SMBSLVC.
This register is described on page 135 (SMBUS SLAVE COMMAND). Registers are
accessible using PCI configuration registers. I have tried this code before
enabling interrupts without success:
pci_write_config_word(dev, SMBSLVC, 0x2c); // synaptics
I don't know if this PDF is relevant for AMD. Newest documentation from
AMD,
which i found is:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.amd.com%2Fsystem%2Ffiles%2FTechDocs%2F55072_AMD_Family_15h_Models_70h-7Fh_BKDG.pdf&data=04%7C01%7Cmario.limonciello%40amd.com%7Cb813c9d7934b4bb971dc08d9d5c610a4%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637775869527091018%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C2000&sdata=OYtn%2FisOR1uHzWVmre9wdIuFhD3PCaHqP2NTRrTh07A%3D&reserved=0
This document describes SMBusSlaveControl on same address (0x08) and
SlaveEnable
looks almost identical.
The interesting part is:
"address that matches the host controller slave port of 10h, a command
field
that matches the SMBus slave control register, and a match of corresponding
enabled events"
Slave device should send address 10h automatically. Enabled events can
be set
using SMBusSlaveEvent register. I have enabled all (set 0xff to 0x0a / 0x0b
registers), but i don't know how to set "command field". There is no
register
named "command field". Intel has SMBSLVC, but i can't find corresponding
register on AMD.
I think "SMBUSx11 I2CCommand" may be what you're looking for.
Constant activity on I2C pins can be repeated host notify request from
synaptics.
Last interesting fact:
I have recorded register value (except 0x02 and 0x07) after each SMBus
transaction. This is from last 2 transactions:
0200 0004 5801 0000 0fa9 00ff ff00 a8aa
0200 0001 5802 0000 0fa9 40ff ff00 a8aa
Every call has SMBusSlaveEvent (register 0x0a) 0x00 except of last
command after
which device is initialized. After this call register has value 0x40. I
have
written 0xff to this register to enable all events in probe function. I
don't
know why it's 0x00 until last transaction.
