On Mon, 20 Jun 2022 01:20:08 +0200 Andy Shevchenko <andy.shevchenko@xxxxxxxxx> wrote: > On Sun, Jun 19, 2022 at 8:59 PM Jonathan Cameron <jic23@xxxxxxxxxx> wrote: > > > > From: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx> > > > > Address an ABI gap for device where the offset of both lines in a > > differential pair may be controlled so as to allow a wider range of > > inputs, but without having any direct effect of the differential > > measurement. > > > > _offset cannot be used as to remain in line with existing usage, > > userspace would be expected to apply it as (_raw + _offset) * scale > > whereas _inputoffset is not. > > Similarly calibbias is expected to tweak the measurement seen, not > > the adjust the two lines of the differential pair. > > > > Needed for in_capacitanceX-capacitanceY_inputoffset for the > > AD7746 CDC driver. > > > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx> > > > > --- > > I''m not entirely happy with the naming on this one, so if anyone > > has a better idea I'm definitely open to it! > > I'm not sure I got the idea behind this, but would be "tare" / > "tarepoint" / alike suitable here? > Hmm I don't think tare maps well as I've never seen it applied to a differential channel like this. Not really seen it much used outside of checkweighing (the mention brought back some horrible memories of debugging software for high speed check weighers :) So to try and explain what this is doing in more depth. This is basically applying a negative offset X to both the P(ostitive) and N(egative) lines. Hence measured capacitance = (P - X) - (N - X) = P - N the aim of X being to keep the signal hitting some internal point on the device within a range that is measurable. The relevant text on the datasheet is: "The CAPDAC can be understood as a negative capacitance connected internally to the CIN pin." "Each of the two input capacitances CX and CY between the EXC and CIN pins must be less than 4 pF (without using the CAPDACs) or must be less than 21 pF and balanced by the CAPDACs. Balancing by the CAPDACs means that both CX–CAPDAC(+) and CY–CAPDAC(–) are less than 4 pF." So basically if you have both sides of the differential pair that are too large (>4 pF) then you can drag them together down to that range by adding negative capacitance. Ouch that's confusing :) Jonathan