On Mon, Jun 20, 2022 at 8:13 PM Jonathan Cameron <jic23@xxxxxxxxxx> wrote: > On Mon, 20 Jun 2022 01:20:08 +0200 > Andy Shevchenko <andy.shevchenko@xxxxxxxxx> wrote: ... > So to try and explain what this is doing in more depth. > > This is basically applying a negative offset X to both the P(ostitive) and > N(egative) lines. Hence > > measured capacitance = (P - X) - (N - X) > = P - N > > the aim of X being to keep the signal hitting some internal point on > the device within a range that is measurable. > > The relevant text on the datasheet is: > > "The CAPDAC can be understood as a negative capacitance > connected internally to the CIN pin." > > "Each of the two input capacitances CX and CY between the EXC > and CIN pins must be less than 4 pF (without using the > CAPDACs) or must be less than 21 pF and balanced by the > CAPDACs. Balancing by the CAPDACs means that both > CX–CAPDAC(+) and CY–CAPDAC(–) are less than 4 pF." > > So basically if you have both sides of the differential pair > that are too large (>4 pF) then you can drag them together > down to that range by adding negative capacitance. Ah, in a long wording it's "measurement window offset". Dunno how to make it shorter. Also, 0-point on the axis in math. -- With Best Regards, Andy Shevchenko
