El Tue, 06-10-2009 a las 23:13 -0400, Mark Lord escribió: > Dunno. Rev.9 == "C0" in Marvell terminology, > and that's the latest/final rev for the 6081 chip, > with most of the PCI-X bugs fixed or worked around. > So not much to go on there. > > The Bus error report was real, though. > But with 3.0gb/sec sata connections, the chip will be > using some different internal clocks and timings, > which could be enough to avoid triggering the PCI errors. > > I guess. Let's hope so, anyway. Our prayers have not been answered :-( I tried several things: - Forcing all the 500GB Seagate drives to 3.0Gbps does not help - Replacing the 500GB drives with 1.5TB drives seems to make the PCI error much less frequent - Moving the controllers to different slots (on different busses) does not help - Happens with both 2.6.26 (from lenny) and 2.6.30 (from sid) - Unplugging one of the controllers appeared to lead to a stable configuration, but yesterday I left the machines reconstructing the arrays and this mornings one of them is not answering to pings ;-( I want to try reducing the frequency of the PCI-X bus, but the BIOS does not seem to provide a setting for it. Is there another way? -- // Bernie Innocenti - http://codewiz.org/ \X/ Sugar Labs - http://sugarlabs.org/ -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
