Hello.
Alan Cox wrote:
But some hardware (namely ULi M5228 in the ULi M1575 "Super South Brige")
behaves in a strange way: it asserts interrupts as edge sensitive. And
because preemptable IRQ handler disables PIC's interrupt, PIC will likely
miss it.
You mean "I've programmed the hardware wrong"
If your M5228 is in native mode it should be generating a level trigger,
providing you've programmed it in full that way. If you have it in legacy
His boot log shows the native mode.
And you don't have much control about the interrupt sense at the IDE
controller side, you can only select legacy/native (which would mean
edge/level IRQs respectively) mode but the BIOS has a freedom to say
misprogram ELCR for the PCI interrupt the controller is using.
mode then it honours IDEIRT and you want the relevant PIC/APIC input set
to level.
What's IDEIRT, some ISA bridge register? And why should one set
[A]PIC to level mode for legacy mode IDE? :-O
How to program an IDE controller out of legacy mode is a public open
standard document.
It's *not* in legacy mode, boot log shows "100# native mode".
It would be great to re-configure the ULi bridge or ULi IDE controller
to behave sanely, but no one knows how or if this is possible at all
(no available specifications).
You need an NDA with ULi for the documentation or I suspect you can
program the APIC or EISA level registers to match assuming its a PCI like
bridge.
He has an OpenPIC, it's PowerPC SoC, so no ELCR either. Anton said to
me that OpenPIC inputs from PCI IRQs are correctly programmed for level
trigger.
Nothe that this ULi chip is on PCI Express, so maybe something is wrong
with how IRQs are delivered over it to the SoC's PCIE controller
MBR, Sergei
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