On Mon, 15 Apr 2019 14:47:12 +0300, Jarkko Nikula wrote: > On 4/12/19 9:42 PM, Jean Delvare wrote: > > Jarkko, are you aware of any setting of the Z370 SMBus controller that > > would block writes to I2C address 0x36? I have a vague memory of some > > setting that aimed at protecting SPD EEPROMs but as I remember it was > > only for address range 0x50-0x57. But I don't remember the details to > > be honest. > > Not sure but specification for SMBus Host Configuration register (0x40) > bit SPD Write Disable (SPDWD) says only 0x50-0x57: > > "When this bit is set to 1, writes to SMBus addresses 50h – 57h are > disabled. Note: This bit is R/WO and will be reset on PLTRST# assertion. > This bit should be set by BIOS to ‘1’. Software can only program this > bit when both the START bit and Host Busy bit are ‘0’; otherwise, the > write may result in undefined behavior." Thanks Jarkko, that's what I found as well when looking specifically in the datasheet of the Z370 chipset. >From the dump provided by Dreamcat4: > 40: 11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 The SPD protection is indeed enabled, as I would expect. But it should not affect SPD page selection which is in address range 0x30-0x37. Anyway it's not possible to disable the SPD protection at run-time, as the bit is Write-Once according to the spreadsheet. I'm out of idea, sorry. The only thing I can suggest is to try different memory modules on this mainboard, and/or these memory modules on another mainboard, to figure out if the problem comes from the memory modules or the mainboard. You could also try your memory modules separately, in case the problem is a bad interaction between the 2. The SPD page selection is kind of a broadcast command, affecting all memory modules at once, and I'm not really sure what would happen if one module behaves OK and the other not. -- Jean Delvare SUSE L3 Support
