On 4/12/19 9:42 PM, Jean Delvare wrote:
On Fri, 12 Apr 2019 19:15:54 +0100, Dreamcat4 wrote:
On Fri, Apr 12, 2019 at 3:43 PM Jean Delvare <jdelvare@xxxxxxx> wrote:
On Thu, 11 Apr 2019 21:08:54 +0100, Dreamcat4 wrote:
[root:/sys/bus/i2c/devices] # cat /sys/bus/i2c/drivers/ee1004/2-0050/eeprom
cat: /sys/bus/i2c/drivers/ee1004/2-0050/eeprom: No such device or address
and that command ^ causes this error msg in dmesg log:
dmesg -w
[12555.445082] ee1004 2-0050: Failed to select page 0 (-6)
OK, so the problem is that the EEPROMs on your memory modules do not
behave the way the ee1004 driver expects. I thought EE1004 was a
standard for all DDR4 modules... I have no satisfactory explanation for
what you observe. Either Crucial used non-standard SPD EEPROMs, or the
SMBus controller is messing up with the commands before they reach the
EEPROMs. But both are pretty unlikely.
Out of curiosity, what's your SMBus controller?
# lspci -nn | grep SMBus
[root:~] 6 # lspci -nn | grep SMBus
00:1f.4 SMBus [0c05]: Intel Corporation 200 Series/Z370 Chipset Family
SMBus Controller [8086:a2a3]
[root:~] #
Jarkko, are you aware of any setting of the Z370 SMBus controller that
would block writes to I2C address 0x36? I have a vague memory of some
setting that aimed at protecting SPD EEPROMs but as I remember it was
only for address range 0x50-0x57. But I don't remember the details to
be honest.
Not sure but specification for SMBus Host Configuration register (0x40)
bit SPD Write Disable (SPDWD) says only 0x50-0x57:
"When this bit is set to 1, writes to SMBus addresses 50h – 57h are
disabled. Note: This bit is R/WO and will be reset on PLTRST# assertion.
This bit should be set by BIOS to ‘1’. Software can only program this
bit when both the START bit and Host Busy bit are ‘0’; otherwise, the
write may result in undefined behavior."
--
Jarkko
