On 7/17/2024 4:23 PM, Bryan O'Donoghue wrote:
On 15/07/2024 11:36, Satya Priya Kakitapalli (Temp) wrote:
This clock is PoR ON clock and expected to be always enabled from HW
perspective, we are just re-ensuring it is ON from probe. Modelling
this clock is unnecessary, and we have been following this approach
for gdsc clock in all the recent chipsets, like for example sm8550
camcc.
Having a difficult time following the logic
- Re-enabling an already enabled always-on clock is necessary
There is no hard requirement to enable it again , but to be on safe side
incase bootloaders disabled this clock, we are enabling it again in probe.
- Modelling the always-on clock in the CCF to park it at XO is
unnecessary
Modelling the clock will cause the CCF to disable the clock in late
init. I have tested on SM8150 by modelling the gdsc clock now and I see
it is getting disabled in late init.
Parking the parent clock(rcg) at XO, doesn't ensure the branch clock to
be ON. If CCF disables the clock it gets disabled.
I think that's a pretty vague argument to be honest.
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bod
