From: 'Christoph Hellwig' > Sent: 08 June 2021 16:32 > > On Tue, Jun 08, 2021 at 03:00:17PM +0000, David Laight wrote: > > It is almost impossible to interface to many ethernet chips without > > either coherent or uncached memory for the descriptor rings. > > The status bits on the transmit ring are particularly problematic. > > > > The receive ring can be done with writeback+invalidate provided you > > fill a cache line at a time. > > It is horrible, but it has been done. Take a look at: > > drivers/net/ethernet/i825xx/lasi_82596.c and > drivers/net/ethernet/seeq/sgiseeq.c I guess that each transmit has to be split into enough fragments that they fill a cache line. That won't work with some (probably old now) devices that require the first fragment to be 64 bytes because it won't back-up the descriptors after a collision. It's all as horrid as a DSP we have that can't receive ethernet frames onto a 4n+2 boundary and doesn't support misaligned accesses. Mind you, Sun's original Sbus ethernet board had to be given a 4n aligned rx buffer and then a misaligned copy done in kernel in order to not drop packets! David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)
