On Wed, May 19, 2021 at 01:48:23PM +0800, Guo Ren wrote: > On Wed, May 19, 2021 at 1:20 PM Christoph Hellwig <hch@xxxxxx> wrote: > > > > On Wed, May 19, 2021 at 05:04:13AM +0000, guoren@xxxxxxxxxx wrote: > > > From: Guo Ren <guoren@xxxxxxxxxxxxxxxxx> > > > > > > The RISC-V ISA doesn't yet specify how to query or modify PMAs, so let > > > vendors define the custom properties of memory regions in PTE. > > > > Err, hell no. The ISA needs to gets this fixed first. Then we can > > talk about alternatives patching things in or trapping in the SBI. > > But if the RISC-V ISA can't get these basic done after years we can't > > support it in Linux at all. > > The patchset just leaves a configuration chance for vendors. Before > RISC-V ISA fixes it, we should give the chance to let vendor solve > their real chip issues. This patch series looks like it might be useful for the StarFive JH7100 [1] [2] too as it has peripherals on a non-coherent interconnect. GMAC, USB and SDIO require that the L2 cache must be manually flushed after DMA operations if the data is intended to be shared with U74 cores [2]. There is the RISC-V Cache Management Operation, or CMO, task group [3] but I am not sure if that can help the SoC's that have already been fabbed like the the D1 and the JH7100. thanks, drew [1] https://github.com/starfive-tech/beaglev_doc/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf [2] https://github.com/starfive-tech/beaglev_doc/blob/main/JH7100%20Cache%20Coherence%20V1.0.pdf [3] https://github.com/riscv/riscv-CMOs
