On Tue, May 18, 2021 at 11:44:35PM -0700, Drew Fustini wrote: > This patch series looks like it might be useful for the StarFive JH7100 > [1] [2] too as it has peripherals on a non-coherent interconnect. GMAC, > USB and SDIO require that the L2 cache must be manually flushed after > DMA operations if the data is intended to be shared with U74 cores [2]. Not too much, given that the SiFive lineage CPUs have an uncached window, that is a totally different way to allocate uncached memory. > There is the RISC-V Cache Management Operation, or CMO, task group [3] > but I am not sure if that can help the SoC's that have already been > fabbed like the the D1 and the JH7100. It does, because unimplemented instructions trap into M-mode, where they can be emulated. Or to summarize things. Non-coherent DMA (and not coherent as title in this series) requires two things: 1) allocating chunks of memory that is marked as not cachable 2) instructions to invalidate and/or writeback cache lines none of which currently exists in RISV-V. Hacking vendor specific cruft into the kernel doesn't scale, as shown perfectly by this series which requires to hard code vendor specific non-standardized extensions in a kernel that makes it specific to that implementation. What we need to do is to standardize a way to do this properly, and then after that figure out a way to quirk in non-compliant implementations in a way that does not harm the general kernel.
