From: Guo Ren <guoren@xxxxxxxxxxxxxxxxx> The RISC-V ISA doesn't yet specify how to query or modify PMAs, so let vendors define the custom properties of memory regions in PTE. This patchset helps SOC vendors to support their own custom interconnect coherent solution with PTE attributes. For example, allwinner D1[1] uses T-HEAD C906 as main processor, C906 has two modes in MMU: - Compatible mode, the same as the definitions in spec. - Enhanced mode, add custom DMA_COHERENT attribute bits in PTE which not mentioned in spec. Allwinner D1 needs the enhanced mode to support the DMA type device with non-coherent interconnect in its SOC. C906 uses BITS(63 - 59) as custom attribute bits in PTE. Here is the config example for Allwinner D1: CONFIG_RISCV_DMA_COHERENT=y CONFIG_RISCV_PAGE_DMA_MASK=0xf800000000000000 CONFIG_RISCV_PAGE_CACHE=0x7000000000000000 CONFIG_RISCV_PAGE_DMA_NONCACHE=0x8000000000000000 Link: https://linux-sunxi.org/D1 [1] Guo Ren (3): riscv: pgtable.h: Fixup _PAGE_CHG_MASK usage riscv: Add DMA_COHERENT for custom PTE attributes riscv: Add SYNC_DMA_FOR_CPU/DEVICE for DMA_COHERENT arch/riscv/Kconfig | 31 ++++++++++++++++++++++++++ arch/riscv/include/asm/pgtable-64.h | 8 ++++--- arch/riscv/include/asm/pgtable-bits.h | 13 ++++++++++- arch/riscv/include/asm/pgtable.h | 26 +++++++++++++++++----- arch/riscv/include/asm/sbi.h | 16 ++++++++++++++ arch/riscv/kernel/sbi.c | 19 ++++++++++++++++ arch/riscv/mm/Makefile | 4 ++++ arch/riscv/mm/dma-mapping.c | 41 +++++++++++++++++++++++++++++++++++ 8 files changed, 148 insertions(+), 10 deletions(-) create mode 100644 arch/riscv/mm/dma-mapping.c -- 2.7.4
