Στις 2021-06-07 06:19, Guo Ren έγραψε:
The C-bit was recently dropped, there is a new proposal for Page Based
Memory Attributes (PBMT) that we can work on / push for.
C-bit still needs discussion, we shouldn't drop it directly.
You can always participate on the discussion on virtmem mailing list.
Raise a page fault won't solve anything. We still need access to the
page with proper performance.
The point is that future hw implementations will be required to return a
page fault in case we tamper with those reserved bits, they won't just
ignore them. Supporting custom values there means supporting
non-compliant implementations.
We need PTEs to provide a non-coherency solution, and only CMO
instructions are not enough. We can't modify so many Linux drivers to
fit it.
From Linux non-coherency view, we need:
- Non-cache + Strong Order PTE attributes to deal with drivers' DMA
descriptors
- Non-cache + weak order to deal with framebuffer drivers
- CMO dma_sync to sync cache with DMA devices
- Userspace icache_sync solution, which prevents calls to S-mode with
IPI fence.i. (Necessary to JIT java scenarios.)
All above are not in spec, but the real chips are done.
(Actually, these have been talked about for more than five years, we
still haven't the uniform idea.)
The idea of C-bit is really important for us which prevents our chips
violates the spec.
Have you checked the PBMT proposal ? It defines (so far) the following
attributes that can be set on PTEs to override the PMAs of the
underlying physical memory:
Bits [62:61]
00 (WB) -> Cacheable, default ordering
01 (NC) -> Noncacheable, default ordering
10 (IO) -> Noncacheable, strong ordering
So it'll cover the use cases you mention.
