On Mon, Jun 7, 2021 at 2:27 PM Christoph Hellwig <hch@xxxxxx> wrote: > > On Mon, Jun 07, 2021 at 11:19:03AM +0800, Guo Ren wrote: > > >From Linux non-coherency view, we need: > > - Non-cache + Strong Order PTE attributes to deal with drivers' DMA descriptors > > - Non-cache + weak order to deal with framebuffer drivers > > - CMO dma_sync to sync cache with DMA devices > > This is not strictly true. At the very minimum you only need cache > invalidation and writeback instructions. For example early parisc > CPUs and some m68knommu SOCs have no support for uncached areas at all, > and Linux works. But to be fair this is very painful and supports only > very limited periphals. So for modern full Linux support some uncahed > memory is advisable. But that doesn't have to be using PTE attributes. > It could also be physical memory regions that are either totally fixed Double/Triple the size of physical memory regions can't be accepted by SOC vendors, because it wastes HW resources. Some cost-down soc interconnects only have 32bit~34bit width of physical address, are you sure you could force them to expand it? (I can't) > or somewhat dynamic. How can HW implement with dynamic modifying PMA? What's the granularity? -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/
