On Thu, May 20, 2021 at 09:45:45AM +0800, Guo Ren wrote: > It's a very big MIPS smell. What's the attribute of the uncached > window? (uncached + strong-order/ uncached + weak, most vendors still > use AXI interconnect, how to deal with a bufferable attribute?) In > fact, customers' drivers use different ways to deal with DMA memory in > non-coherent SOC. Most riscv SOC vendors are from ARM, so giving them > the same way in DMA memory is a smart choice. So using PTE attributes > is more suitable. I'm not saying it is a good idea. Just that apparently this exists in the ASICs.
