From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Here's a (still somewhat rough) series to get rid of al those horrible fuzzy clock checks in the fastset code. We achieve that by feeding back the actual DPLL frequency and actual dotclock into the crtc state. And with fastset made to not suck we can consider allowing seameless M/N changes on eDP panels that support such things. I've given that a quick test here on a TGL and it seemed to work OK. The rough parts: - The DPLL stuff is kinda messy still, a lot of which is due to the dpll_mgr vs. not depending on platform/output type. Maybe it's finally time to start cleaning that mess up... - fastboot is a bit challenging due to rounding behaviour differences between i915 vs. VBIOS/GOP - DSI clock handling is snafu - Didn't polish some of the things fully yet - Might be some stuff I've still overlooked Figured I'd see if there's any feedback, and get CI results for it anyway. Pushed the lot here: https://github.com/vsyrjala/linux.git crtc_clock_compute_8 Ville Syrjälä (26): drm/i915: Split shared dpll .get_dplls() into compute and get phases drm/i915: Do .crtc_compute_clock() earlier drm/i915: Clean up DPLL related debugs drm/i915: Reassign DPLLs only for crtcs going throug .compute_config() drm/i915: Extract PIPE_CONF_CHECK_TIMINGS() drm/i915: Extract PIPE_CONF_CHECK_RECT() drm/i915: Adjust intel_modeset_pipe_config() & co. calling convention drm/i915: s/pipe_config/crtc_state/ drm/i915: Improve modeset debugs drm/i915: Extract intel_crtc_dotclock() drm/i915: Introduce struct iclkip_params drm/i915: Feed the DPLL output freq back into crtc_state drm/i915: Compute clocks earlier drm/i915: Skip FDI vs. dotclock sanity check during readout drm/i915: Make M/N checks non-fuzzy drm/i915: Make all clock checks non-fuzzy drm/i915: Set active dpll early for icl+ drm/i915: Nuke fastet state copy hacks drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled drm/i915: Check hw.enable and hw.active in intel_pipe_config_compare() drm/i915: Add intel_panel_highest_mode() drm/i915: Allow M/N change during fastset on bdw+ drm/i915: Require an exact DP link freq match for the DG2 PLL drm/i915: Use a fixed N value always drm/i915: Round to closest in M/N calculations drm/i915: Round TMDS clock to nearest drivers/gpu/drm/i915/display/intel_crt.c | 3 + drivers/gpu/drm/i915/display/intel_ddi.c | 21 +- drivers/gpu/drm/i915/display/intel_display.c | 376 +++++++----------- drivers/gpu/drm/i915/display/intel_display.h | 2 +- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 36 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +- drivers/gpu/drm/i915/display/intel_dpll.c | 156 +++++--- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 373 ++++++++++++----- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 3 + drivers/gpu/drm/i915/display/intel_fdi.c | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/display/intel_panel.c | 15 + drivers/gpu/drm/i915/display/intel_panel.h | 3 + .../gpu/drm/i915/display/intel_pch_refclk.c | 100 +++-- .../gpu/drm/i915/display/intel_pch_refclk.h | 1 + drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +- 17 files changed, 650 insertions(+), 449 deletions(-) -- 2.35.1
