✗ Fi.CI.BAT: failure for drm/i915: Make fastset not suck and allow seamless M/N changes (rev3)

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Title: Project List - Patchwork
Patch Details
Series:drm/i915: Make fastset not suck and allow seamless M/N changes (rev3)
URL:https://patchwork.freedesktop.org/series/103491/
State:failure
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/index.html

CI Bug Log - changes from CI_DRM_11607 -> Patchwork_103491v3

Summary

FAILURE

Serious unknown changes coming with Patchwork_103491v3 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_103491v3, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/index.html

Participating hosts (41 -> 43)

Additional (4): bat-adlm-1 bat-dg2-9 bat-dg1-6 bat-dg1-5
Missing (2): bat-rpls-1 fi-bsw-cyan

Possible new issues

Here are the unknown changes that may have been introduced in Patchwork_103491v3:

CI changes

Possible regressions

Known issues

Here are the changes found in Patchwork_103491v3 that come from known issues:

IGT changes

Issues hit

Possible fixes

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Build changes

CI-20190529: 20190529
CI_DRM_11607: b0f0de5bb000952abb29696adb93f289e49b129c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6465: f6bb4399881a806fbff75ce3df89b60286d55917 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103491v3: b0f0de5bb000952abb29696adb93f289e49b129c @ git://anongit.freedesktop.org/gfx-ci/linux

Linux commits

e47ee538fdac drm/i915: Round TMDS clock to nearest
2c15dc8d0431 drm/i915: Round to closest in M/N calculations
ed84fb347dbe drm/i915: Use a fixed N value always
2f23a795f9b3 drm/i915: Require an exact DP link freq match for the DG2 PLL
f21ef6758edc drm/i915: Allow M/N change during fastset on bdw+
4cee8cdbf92a drm/i915: Add intel_panel_highest_mode()
d8c4c0523cf5 drm/i915: Check hw.enable and hw.active in intel_pipe_config_compare()
ea029822b164 drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled
deb76f94c1c8 drm/i915: Nuke fastet state copy hacks
50134a3f553e drm/i915: Set active dpll early for icl+
2fecea3f92c8 drm/i915: Make all clock checks non-fuzzy
7a3196e310fe drm/i915: Make M/N checks non-fuzzy
88adc6978813 drm/i915: Skip FDI vs. dotclock sanity check during readout
47a7e822fa39 drm/i915: Compute clocks earlier
f0669cd95559 drm/i915: Feed the DPLL output freq back into crtc_state
86073c76b21a drm/i915: Introduce struct iclkip_params
62eb500d0db0 drm/i915: Extract intel_crtc_dotclock()
8794835b216b drm/i915: Improve modeset debugs
e8d85ab5494d drm/i915: s/pipe_config/crtc_state/
ae9354c7d071 drm/i915: Adjust intel_modeset_pipe_config() & co. calling convention
92259ea0a65e drm/i915: Extract PIPE_CONF_CHECK_RECT()
40c6ace45fcd drm/i915: Extract PIPE_CONF_CHECK_TIMINGS()
3443b586e221 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
42d3ab605cbd drm/i915: Clean up DPLL related debugs
fb6021bb240a drm/i915: Do .crtc_compute_clock() earlier
b8d3f58a88d6 drm/i915: Split shared dpll .get_dplls() into compute and get phases


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