From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Currently we're unmasking some random looking bits in HWSTAM
on gen3/4/5. The two bits we apparently unmask are 0 and 12,
and also bits 16-31 on gen4/5.
What those bits do depends on the gen as follows:
bit 0: Breakpoint (gen2), ASLE (gen3), reserved (gen4), render user interrupt (gen5)
bit 12: Sync flush statusa (gen2-4), reserved (gen5)
bit 16-31: The ones that can unmasked seem to be mostly some
display stuff on gen4. Bit 18 is the PIPE_CONTROL notify,
which might be the only intresting one. On gen5 all the
bits are reserved.
So I don't know whether we actually depend on that status page write
somehow. Extra seqno coherency by accident perhaps? Except we don't
even unmask the user interrupt bit in HWSTAM except on gen5, and
sync flush isn't something we use normally, so seems unlikely. So
let's just assume we don't need any of this and mask everything in
HWSTAM.
>From gen6 onwards there's a separate HWSTAM for each engine, and so
we deal with them during the engine setup.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/i915_irq.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2b8aeb79a7a8..f55f1b61d117 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3027,7 +3027,8 @@ static void ironlake_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- I915_WRITE(HWSTAM, 0xffffffff);
+ if (IS_GEN5(dev_priv))
+ I915_WRITE(HWSTAM, 0xffffffff);
GEN3_IRQ_RESET(DE);
if (IS_GEN7(dev_priv))
@@ -3390,8 +3391,6 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
dev_priv->irq_mask = ~display_mask;
- I915_WRITE(HWSTAM, 0xeffe);
-
ibx_irq_pre_postinstall(dev);
GEN3_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
@@ -3594,8 +3593,6 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
gen5_gt_irq_reset(dev_priv);
- I915_WRITE(HWSTAM, 0xffffffff);
-
spin_lock_irq(&dev_priv->irq_lock);
if (dev_priv->display_irqs_enabled)
vlv_display_irq_reset(dev_priv);
@@ -3630,6 +3627,8 @@ static void i8xx_irq_preinstall(struct drm_device * dev)
i9xx_pipestat_irq_reset(dev_priv);
+ I915_WRITE16(HWSTAM, 0xffff);
+
GEN2_IRQ_RESET();
}
@@ -3779,6 +3778,8 @@ static void i8xx_irq_uninstall(struct drm_device * dev)
i9xx_pipestat_irq_reset(dev_priv);
+ I915_WRITE16(HWSTAM, 0xffff);
+
GEN2_IRQ_RESET();
}
@@ -3793,7 +3794,7 @@ static void i915_irq_preinstall(struct drm_device * dev)
i9xx_pipestat_irq_reset(dev_priv);
- I915_WRITE(HWSTAM, 0xffffeffe);
+ I915_WRITE(HWSTAM, 0xffffffff);
GEN3_IRQ_RESET();
}
@@ -4003,7 +4004,7 @@ static void i965_irq_preinstall(struct drm_device * dev)
i9xx_pipestat_irq_reset(dev_priv);
- I915_WRITE(HWSTAM, 0xeffe);
+ I915_WRITE(HWSTAM, 0xffffffff);
GEN3_IRQ_RESET();
}
--
2.13.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
