Quoting ville.syrjala@xxxxxxxxxxxxxxx (2017-06-22 12:55:49) > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Currently we're unmasking some random looking bits in HWSTAM > on gen3/4/5. The two bits we apparently unmask are 0 and 12, > and also bits 16-31 on gen4/5. > What those bits do depends on the gen as follows: > bit 0: Breakpoint (gen2), ASLE (gen3), reserved (gen4), render user interrupt (gen5) > bit 12: Sync flush statusa (gen2-4), reserved (gen5) > bit 16-31: The ones that can unmasked seem to be mostly some > display stuff on gen4. Bit 18 is the PIPE_CONTROL notify, > which might be the only intresting one. On gen5 all the > bits are reserved. > > So I don't know whether we actually depend on that status page write > somehow. Extra seqno coherency by accident perhaps? Except we don't > even unmask the user interrupt bit in HWSTAM except on gen5, and > sync flush isn't something we use normally, so seems unlikely. So > let's just assume we don't need any of this and mask everything in > HWSTAM. Once upon a time we were discussing that HWSTAM might give us better seqno coherency. The conclusion for gen6, at least iirc, was that the HWSTAM was unordered with the MI_STORE_DWORD. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
