On Thu, Jan 30, 2020 at 11:57:11AM +0100, Stefan Franke wrote: > My approach was: group all bits which may change simultaneously into one CC > reg each > > This may result into one or more CC regs . > I got two of these > > Create at least a mode for each CC reg for each used combination > I got two modes for the first CC reg: one to reflect eq/ne and one > mode for all other > And one mode for the second CC reg, which covers all conditions > > Then I coded the cbranch/cstore expands accordingly > > A CC reg is either used in a branch or sets the boolean value 0/1 in a > DI/SI/HI/QI register. That all sounds fine. > You'll may do more work later, if you want to support insn resulting by the > combine pass, e.g. testing single bits... The combine pass helpfully tells you (in its dump file, use -fdump-rtl-combine-all) what it tried to do, what it wants the patterns in your machine description to look like. You can fight it, or work *with* it ;-) The code you emit for cbranch/cstore/ctrap does not have to be very optimised, it is hard enough to get it correct; all the usual RTL passes will optimise it just fine, if your RTL instruction patterns are close to the actual machine instructions. Segher
