Hi! On Tue, Jan 28, 2020 at 11:22:08AM +0100, Henri Cloetens wrote: > - The machine has a CC mode condition code register. It has 12 condition > code bits, > split in 4 CC fields. > - field 0 : bits 2:0 > field 1 : bits 5:3 > field 2 : bits 8:6 > field 3 : bits 11:9 So this is similar to Power (rs6000), where we have eight 4-bit CR fields modelled in GCC (there are machine insns that act on one bit, or on all 32 bits, as well). In GCC, there are eight registers. > So good so far ... but I get a compiler error in the routine > "validate_subreg" > Of course, the OSIZE is not a multiple of the REGSIZE. The REGSIZE is > 3 bits. Yes. A subreg with a non-zero offset has an offset counted in *bytes*. So modelling this with subregs the way you do cannot work. Segher
