Hello Segher, all,
- It is indeed true subreg only works on bytes.
- So, I changed the declaration:
a. I declared all 12 condition code bits as BYTES (QI)
b. I split it in 4 CC fields (cfr below), and declared each of these
as SI.
- Then, the compare addresses the CC field in SI mode, the branch in QI
mode, and all goes well. I mean, it does not matter if I declare SI
or BI, because
the compare instruction only writes 0 or 1, and the branch
instruction tests only
for 0 or 1.
- With all goes well, I mean, gcc-9.2.0 correctly writes the CC field,
and then correctly
picks the correct subreg for the branch.
- BUT ... the test still fails. I refer here to "emit-rtl.c", function
validate_subreg() in gcc-9.2.0
the test on line 1024. It is commented why it fails :
OSIZE is not a multiple of REGSIZE. The intend here is to have
REGSIZE as byte, but the
routine calculates REGSIZE as REGMODE_NATURAL_SIZE(imode).
I do not understand this. I mean, imode is SImode, but in the backend
description, it is
described that 4 registers of the CC field are necessary to hold an
operand of type SImode.
- Is this a bug ?, or, what did I wrong ?.
Best Regards,
Henri/
On 01/28/2020 02:40 PM, Segher Boessenkool wrote:
Hi!
On Tue, Jan 28, 2020 at 11:22:08AM +0100, Henri Cloetens wrote:
- The machine has a CC mode condition code register. It has 12 condition
code bits,
split in 4 CC fields.
- field 0 : bits 2:0
field 1 : bits 5:3
field 2 : bits 8:6
field 3 : bits 11:9
So this is similar to Power (rs6000), where we have eight 4-bit CR fields
modelled in GCC (there are machine insns that act on one bit, or on all
32 bits, as well). In GCC, there are eight registers.
So good so far ... but I get a compiler error in the routine
"validate_subreg"
Of course, the OSIZE is not a multiple of the REGSIZE. The REGSIZE is
3 bits.
Yes. A subreg with a non-zero offset has an offset counted in *bytes*.
So modelling this with subregs the way you do cannot work.
Segher
