Hello all,
I am writing code for my target, and I have an issue.
- The machine has a CC mode condition code register. It has 12 condition
code bits,
split in 4 CC fields.
- field 0 : bits 2:0
field 1 : bits 5:3
field 2 : bits 8:6
field 3 : bits 11:9
- Now, in the machine instructions, these bits are used in 2 types of
instructions:
a. In compare instructions. These set
field bit 0 = "equal"
field bit 1 = "less than"
field bit 2 = "greater than"
b. In logical instructions. There, every bit represents a bool,
either true or false.
- In the machine description, I have described them as 12 bits of
BImode, whereof there
is a "super mode", CCmode, but to keep an operand of type CCmode in
these fields,
it needs 3 consecutive registers, starting at 0,3,6,9.
(I think I described this correctly.)
- In the define_split of the "cbranch" operation, then first
(a.) a "compare" is invoked, with any of these registers in the
CCmode.
(b.) The relevant subreg is selected, and the relevant register of
BImode is passed to the
define_insn that needs to output the branch.
So good so far ... but I get a compiler error in the routine
"validate_subreg"
(gcc 9.2.0, emit-rtl.c, line 1000). There, I find the comments:
//* For pseudo registers, we want most of the same checks. Namely:
Assume that the pseudo register will be allocated to hard registers
that can hold REGSIZE bytes each. If OSIZE is not a multiple of
REGSIZE,
the remainder must correspond to the lowpart of the containing hard
register. If BYTES_BIG_ENDIAN, the lowpart is at the highest offset,
otherwise it is at the lowest offset.
Given that we've already checked the mode and offset alignment,
we only have to check subblock subregs here. *//
Of course, the OSIZE is not a multiple of the REGSIZE. The REGSIZE is
3 bits.
(That is the CCmode)( (it misunderstood it for 4 bits, still need to
trace that),
the OSIZE is 1 bit (BImode), and I want subreg 1, ie the second bit of
the REGSIZE
being 3 bits.
My debug dump says:
big endian: 0
offset : 1
block_size : 4
start_reg 0
offset_within_reg 1
osize : 1
isize : 4
Best Regards,
Henri.
