> -----Ursprüngliche Nachricht----- > Von: gcc-help-owner@xxxxxxxxxxx <gcc-help-owner@xxxxxxxxxxx> Im > Auftrag von Segher Boessenkool > Gesendet: Donnerstag, 30. Januar 2020 11:48 > An: Henri Cloetens <henri.cloetens@xxxxxxxxxx> > Cc: gcc-help@xxxxxxxxxxx > Betreff: Re: Issue with subregs > > Hi! > > On Thu, Jan 30, 2020 at 11:19:18AM +0100, Henri Cloetens wrote: > > - It is indeed true subreg only works on bytes. > > - So, I changed the declaration: > > a. I declared all 12 condition code bits as BYTES (QI) > > That's not going to work. The separate 3-bit fields are still at offsets 0, 3, 6, 9 > bit. You cannot use subregs to access them. > > > b. I split it in 4 CC fields (cfr below), and declared each of these > > as SI. > > Why not as CCmode? That's what they are, after all. > > > - Then, the compare addresses the CC field in SI mode, the branch in > > QI > > mode, and all goes well. I mean, it does not matter if I declare SI > > or BI, because > > the compare instruction only writes 0 or 1, and the branch > > instruction tests only > > for 0 or 1. > > Or do the compare insns only set single bits? Not (e.g.) all of "less than", > "equal to", "greater than" at once? > > > Segher My approach was: group all bits which may change simultaneously into one CC reg each This may result into one or more CC regs . I got two of these Create at least a mode for each CC reg for each used combination I got two modes for the first CC reg: one to reflect eq/ne and one mode for all other And one mode for the second CC reg, which covers all conditions Then I coded the cbranch/cstore expands accordingly A CC reg is either used in a branch or sets the boolean value 0/1 in a DI/SI/HI/QI register. You'll may do more work later, if you want to support insn resulting by the combine pass, e.g. testing single bits... cheers Stefan
