Re: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 not defined on aarch64

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On 29/06/17 19:35, Alexander Monakov wrote:
> I think a practical approach is to give the user a degree of control by
> introducing a tri-state compiler option controlling how double-word atomics
> are to be emitted:

[snip]

I will properly reply to the above in a bit but I thought it might help
give a users view of things.  Obviously, only one user with his own
particular view, but it can help to have concrete examples.

In lock-free data structures, the main use of DWCAS is to have a counter
along with a pointer, to solve ABA.  The counter is a version number for
the pointer, and is incremented whenever the pointer is modified.

The counter is the first element in the counter-pointer array.  It is
always read first, and it is a single registers worth of data, so it is
read correctly.

Of course, the pointer can then change after we've read the version but
before we're read the pointer - but it just doesn't matter because we
*have* the version already (for who-ever wrote to the pointer will also
have updated the version counter first).

This means when we come to write back using that pointer, our DWCAS will
fail (as it should do) because the counter-pointer pair have been
modified by someone else since we read them (so we have to iterate again
and try once more to do whatever it was we were trying to do - we will
try to read the counter-pointer pair again).

On IA64, there is no DWCAS.  There is a wonderful little single-word
compare, double-word write.  It's all that I need - for all I need to do
is compare the version counter.

Actually, I wonder what GCC does for CAS/DWCAS on IA64?  their
instruction doesn't fit the CAS/DWCAS paradym!

So for me, the fact the double-word reads are not read together is
absolutely irrelevant.  It doesn't affect me at all.





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