Re: mlock in cache

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On Fri, 2013-08-02 at 20:01 +0100, Christos wrote:
> On 08/02/2013 07:14 PM, Oleg Endo wrote:
> > In addition to that, memory accesses can either go through the cache or
> > bypass the cache (there are special bits in the address for that when
> > accessing memory without MMU, or settings in MMU pages).
> > With these low level things something like what you described above
> > could be constructed, but probably it will be difficult to do so in a
> > multi tasking environment.

> Why do you say so? I ask you because my main interest is a 
> multiprocessing/multicore system.
> I can't see why you can't do that if you work at a very low level, like 
> the one you mentioned, as I said previously.

Even when you do it at the very low level (all of the SH4 instructions
mentioned above work in user space), in preemptive multi tasking systems
the code that does manual cache control might be interrupted by
something else (e.g. thread/process context switch or interrupt) and
that other code can potentially trash the cache.  The original intention
for such cache control instructions was efficient streaming data
processing, so it's OK if you don't have 100% control over the cache all
the time and hit a cache miss occasionally.  For the things you've
mentioned you'd probably need to disable preemption at all levels
(disable interrupts) which can be done in kernel space (with some
potential negative side effects).
This should work on multi-processor systems, if the cache control
instructions refer to the L1 and L1 caches are not synchronized among
processors.  With multi-core systems it's probably going to be a bit
tricky due to cache coherency mechanisms.

> > If GCC doesn't have a built-in function
> > ready for the particular special instruction it can be issued rather
> > easily with inline asm.
> Well, I think I mentioned this aspect before and it really has to do 
> with finding the necessary asm directives.
> > Also, there's no guarantee that e.g.
> > __builtin_prefetch will actually emit a prefetch instruction.
> Thanks a lot for that because it was another question of mine. Do you 
> know at which part of the official documentation this thing is mentioned?

No idea, sorry.

Cheers,
Oleg





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