On 08/02/2013 04:20 PM, Florian Weimer wrote:
Most CPUs just do not support this.Some hardware transaction memory implementations perform cache line locking as an implementation detail.
Do you know any of them as an example? -- Christos Tsopokis
On 08/02/2013 04:20 PM, Florian Weimer wrote:
Most CPUs just do not support this.Some hardware transaction memory implementations perform cache line locking as an implementation detail.
Do you know any of them as an example? -- Christos Tsopokis