On Fri, Aug 2, 2013 at 8:51 AM, Christos <xristos.tsop@xxxxxxxxx> wrote: > On 08/02/2013 04:40 PM, Florian Weimer wrote: >> >> On 08/02/2013 05:38 PM, Christos wrote: >>> >>> On 08/02/2013 04:20 PM, Florian Weimer wrote: >>>> >>>> Most CPUs just do not support this. >>>> >>>> Some hardware transaction memory implementations perform cache line >>>> locking as an implementation detail. >>> >>> >>> Do you know any of them as an example? >> >> >> Intel Haswell, perhaps. >> > > Well I'll search through it but for example in arm architecture there is > this: > http://sourceware.org/sid/component-docs/hw-cache.html#behavior-line%20locking > > What I'm thinking of is if prefetching works like a force just as a > suggestion to the cpu to cache some page. Because if it's the latter then > you can't rely on repetitive prefetching to achieve it... > > -- > Christos Tsopokis > Can I naively ask what the purpose is of forcing this data to be in cache all the time? If you use the data often enough for this to be useful, it will already be in cache. If you don't, you benefit by having it not be in cache. Brian
