Pan ruochen wrote: >> No. >> >> It is separate from the caches and was intended to coalesce adjacent writes >> into a single wider write. It had the problem that it could end up >> reordering the writes under some circumstances even through uncached >> portions of the address space. >> >> David Daney >> > > Is there any online document introducing hardware write reordering > about MIPS? I want to have a read > to get more details. Each MIPS CPU is different. Read the hardware manual and errata for the particular CPU you are interested in. David Daney
