| Bug ID | 98821 |
|---|---|
| Summary | [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 clock gate feature" sets MCLK on highest state |
| Product | DRI |
| Version | DRI git |
| Hardware | Other |
| OS | All |
| Status | NEW |
| Severity | normal |
| Priority | medium |
| Component | DRM/AMDgpu |
| Assignee | dri-devel@lists.freedesktop.org |
| Reporter | arek.rusi@gmail.com |
Hi, before this commit MCLK works ok, reverting did the job. [1] drm/amdgpu: refine uvd 6.0 clock gate feature https://cgit.freedesktop.org/~agd5f/linux/commit/?h=drm-next-4.10-wip&id=1b7eab1f8346ab3b8e4fc54882306340a84497a8 There is two stages for this issue: [1] MCLK is HIGH (maybe more power consumption) [2] MCLK is LOW - performance hit. [1]for idle (two displays but only one is active) cat /sys/class/drm/card0/device/pp_dpm_sclk 0: 300Mhz * 1: 466Mhz 2: 751Mhz 3: 1019Mhz 4: 1074Mhz 5: 1126Mhz 6: 1169Mhz 7: 1260Mhz cat /sys/class/drm/card0/device/pp_dpm_mclk 0: 300Mhz 1: 2000Mhz * [2]drm/amdgpu:impl vgt_flush for VI(V5) https://cgit.freedesktop.org/~agd5f/linux/commit/?h=drm-next-4.10-wip&id=ddfe1db18752b08d88d81cb7b661e1f982fc5d04 MCLK is set to LOWEST state (300MHz) and nothing can change that until revert [1].
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