[Bug 98821] [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 clock gate feature" sets MCLK on highest state

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Comment # 11 on bug 98821 from
(In reply to Alex Deucher from comment #10)
> Created attachment 128168 [details] [review] [review]
> fix
> 
> This patch fixes the issue.

not for me...
"always 300MHz" still here.


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