Jan-Benedict Glaw wrote: > On Thu, 2007-08-30 23:43:26 +0200, Jan-Benedict Glaw <jbglaw@xxxxxxxxxx> wrote: >> Just out of interest, I ordered another, similar card (Ultron >> Octosound 7.1, lspci: "C-Media Electronics Inc CM8738 (rev 10)", >> /proc/asound/cards: "C-Media PCI CMI8738-MC8 (model 68)") I have the same chip here. >> [...] >> After the FLAC ended, I fired up speaker-test again (and of course >> switched off "Four Channel Mode".) This time, it's different than >> before: front center/LFE, front left/right and side left/right are >> okay, but rear right/left are highly distorted. I can reproduce this. > Register 0x04 > ~~~~~~~~~~~~~ > Before: 0x07 << CM_ASFC_SHIFT | 0x00 << CM_DSFC_SHIFT | CM_BREQ > After: 0x07 << CM_ASFC_SHIFT | 0x07 << CM_DSFC_SHIFT | CM_BREQ > > (DAC Sample Frequency changed) 0 is the power-on default of 5512 Hz, 7 is 48 kHz. "DAC" and "ADC" aren't quite the correct names, both DMA channels can be used for either playback and capture, and the driver uses one for stereo and the other for multichannel playback. Does the FLAC file have a sample rate of 44.1 kHz or 48 kHz? > Register 0x08 > ~~~~~~~~~~~~~ > Before: CM_CHB3D5C | CM_SPDIF_SELECT1 | 0x03 << CM_CH1FMT_MASK | 0x00 << CM_CH0FMT_SHIFT > After: CM_CHB3D5C | CM_SPDIF_SELECT1 | 0x03 << CM_CH1FMT_MASK | 0x03 << CM_CH0FMT_SHIFT > > (Ch0 Format changed) 0 is 8-bit mono, 3 is 16-bit stereo (or more than two channels). > Register 0x18 > ~~~~~~~~~~~~~ > Before: CM_TXVX | CM_FM_EN | CM_AC3EN2 | CM_VIDWPPRT | CM_ENCENTER | CM_FLINKOFF > After: CM_TXVX | CM_FM_EN | CM_AC3EN2 | CM_VIDWPPRT | CM_SPDF_AC97 | CM_ENCENTER | CM_FLINKOFF > > (SPDIF/Out changed from 44.1kHz to 48kHz) > > My guess is that the change to SPDIF/Out frequency and DAC Sample > Frequency are annoying at best, but irrelevant here. Am I probably > right that the changed ch0 format is the cause of the distortion? I think it's the sample rate. It seems I can 'cure' the distortion by playing a 48 kHz file before running speaker-test. Can you confirm this? The chip has two sample rate registers (ASFC and DSFC), and these are internally mapped to three destinations (front+side+center DACs, rear DAC, capture ADC) depending on the state of a bunch of other bits. I guess the driver doesn't handle these bits correctly so that the rear sample rate is still the old value (although the two xSFC registers appear to have the correct value). Regards, Clemens ------------------------------------------------------------------------- This SF.net email is sponsored by: Splunk Inc. Still grepping through log files to find problems? Stop. Now Search log events and configuration files using AJAX and a browser. Download your FREE copy of Splunk now >> http://get.splunk.com/ _______________________________________________ Alsa-user mailing list Alsa-user@xxxxxxxxxxxxxxxxxxxxx https://lists.sourceforge.net/lists/listinfo/alsa-user
