From: Edoardo Scaglia <scaglia@xxxxxxxxxxxx> The ROM base address in the 9x5 processors lives at 1M, not 4M, where SMD is, as defined later in the same file. The ROM includes some tables that are used to build error-correction data for NAND memory. By using the wrong address, we get wrong data and the result is undetected bit flips (data at 0x408000 is all zeroes). Thus, even though our kernel was fixing bit errors in NAND, barebox was not fixing them. With UBI (our situation) we got I/O errors because the checksum verification for data nodes failed. Using the proper address corrects the problem: barebox reports a "bitflip" message, consistent with the kernel message for the same file, and the files are properly loaded and booted. Note: the kernel has the same wrong define, but then the magic number 0x00108000 as spelled in arch/arm/boot/dts/at91sam9x5.dtsi is used instead of the symbolic name. Signed-off-by: Edoardo Scaglia <scaglia@xxxxxxxxxxxx> Signed-off-by: Federico Braghiroli <braghiroli@xxxxxxxxxxxx> Signed-off-by: Alessndro Rubini <rubini@xxxxxxxxx> --- arch/arm/mach-at91/include/mach/at91sam9x5.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h index 7ba2e3b..e230577 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h @@ -144,7 +144,7 @@ #define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */ #define AT91SAM9X5_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */ -#define AT91SAM9X5_ROM_BASE 0x00400000 /* Internal ROM base address */ +#define AT91SAM9X5_ROM_BASE 0x00100000 /* Internal ROM base address */ #define AT91SAM9X5_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ #define AT91SAM9X5_SMD_BASE 0x00400000 /* SMD Controller */ -- 1.7.7.2 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
