On Fri, 4 Sep 2015 08:20:48 +0200
Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> wrote:
> On Fri, Aug 28, 2015 at 06:46:14PM +0300, Antony Pavlov wrote:
> > On Fri, 28 Aug 2015 08:34:32 +0200
> > Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> wrote:
> >
> > > On Fri, Aug 28, 2015 at 01:24:04AM +0300, Antony Pavlov wrote:
> > > > N.B. phys_to_virt() translates phys address
> > > > to KSEG1 (uncached) address as barebox mips
> > > > has no cache support.
> > >
> > > What would it take to implement cache support for mips?
> > lack of the cache support is critical problem for current barebox mips support.
> > I'm planning to add cache support in several weeks.
> > This task needs much test efforts for different boards.
> >
> > Anyway I can't carry out cache adding work at one.
> > But adding virt_to_phys and DMA support will help to add cache support one day anyway.
>
> Looking at this again the virt_to_phys/phys_to_virt macros are not
> necessary. dma_alloc_coherent() already returns both the virtual address
> and the DMA address. It should be possible to replace DMA_ADDRESS_BROKEN
> in the ehci driver with a real pointer and use it appropriatly in the
> driver.
Here is a fragment of drivers/usb/host/ehci-hcd.c:
while (td != (void *)QT_NEXT_TERMINATE) {
qh->qt_next = td->qt_next;
td = (void *)hc32_to_cpu(qh->qt_next);
}
qh->qt_next contains physical memory address for EHCI controller,
so after 'td = (void *)hc32_to_cpu(qh->qt_next)' contains physical address.
But latter we can use 'td->qt_next'. If physical address != virtual address
then we will fail. So we need addition phys_to_virt() call here.
Some addition workaround is needed here because phys_to_virt(QT_NEXT_TERMINATE) != QT_NEXT_TERMINATE.
--
--
Best regards,
Antony Pavlov
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