On Fri, 28 Aug 2015 08:34:32 +0200 Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> wrote: > On Fri, Aug 28, 2015 at 01:24:04AM +0300, Antony Pavlov wrote: > > N.B. phys_to_virt() translates phys address > > to KSEG1 (uncached) address as barebox mips > > has no cache support. > > What would it take to implement cache support for mips? lack of the cache support is critical problem for current barebox mips support. I'm planning to add cache support in several weeks. This task needs much test efforts for different boards. Anyway I can't carry out cache adding work at one. But adding virt_to_phys and DMA support will help to add cache support one day anyway. > The u-boot mips > cache code seems quite straight forward. AFAIR u-boot has only mips L1 cache support. AFAIK Paul Burton works on adding L2 cache support but current mainline u-boot repo has no such code. > With cache support you could > use several drivers as they are and wouldn't have to introduce > physical/virtual translations. I'm afraid these translations will be > broken quite soon as they get tested only on Mips. I hope somebody will test my EHCI patch on ARM :) -- Best regards, Antony Pavlov _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
