On Fri, Aug 28, 2015 at 06:46:14PM +0300, Antony Pavlov wrote: > On Fri, 28 Aug 2015 08:34:32 +0200 > Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> wrote: > > > On Fri, Aug 28, 2015 at 01:24:04AM +0300, Antony Pavlov wrote: > > > N.B. phys_to_virt() translates phys address > > > to KSEG1 (uncached) address as barebox mips > > > has no cache support. > > > > What would it take to implement cache support for mips? > lack of the cache support is critical problem for current barebox mips support. > I'm planning to add cache support in several weeks. > This task needs much test efforts for different boards. > > Anyway I can't carry out cache adding work at one. > But adding virt_to_phys and DMA support will help to add cache support one day anyway. Looking at this again the virt_to_phys/phys_to_virt macros are not necessary. dma_alloc_coherent() already returns both the virtual address and the DMA address. It should be possible to replace DMA_ADDRESS_BROKEN in the ehci driver with a real pointer and use it appropriatly in the driver. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
