On Tue, Mar 19, 2013 at 10:21:57AM +0100, Steffen Trumtrar wrote:
> Add basic support for the Xilinx Zynq-7000 EPP architecture.
> The Zynq-7000 is an embedded processing platform that combines a Cortex A9
> dualcore MPSoC with an Artix-7 FPGA.
>
> Signed-off-by: Steffen Trumtrar <s.trumtrar@xxxxxxxxxxxxxx>
> ---
[..]
> diff --git a/arch/arm/mach-zynq/include/mach/zynq-flash-header.h b/arch/arm/mach-zynq/include/mach/zynq-flash-header.h
> new file mode 100644
> index 0000000..a0251cb
> --- /dev/null
> +++ b/arch/arm/mach-zynq/include/mach/zynq-flash-header.h
> @@ -0,0 +1,40 @@
> +#ifndef __MACH_FLASH_HEADER_H
> +#define __MACH_FLASH_HEADER_H
> +
> +#include <asm-generic/sections.h>
> +
> +#define __flash_header_start __section(.flash_header_start)
> +
> +#define __flash_header_section __section(.flash_header_0x0)
> +#define __ps7reg_entry_section __section(.ps7reg_entry_0x0A0)
> +#define __image_len_section __section(.image_len_0x08c0)
> +#define FLASH_HEADER_OFFSET 0x0
> +#define IMAGE_OFFSET 0x8c0
> +
> +#define DEST_BASE 0x8c0
> +#define FLASH_HEADER_BASE (DEST_BASE + FLASH_HEADER_OFFSET)
> +
> +struct zynq_reg_entry {
> + __le32 addr;
> + __le32 val;
> +};
> +
> +#define WIDTH_DETECTION_MAGIC 0xAA995566
> +#define IMAGE_IDENTIFICATION 0x584C4E58 /* "XLNX" */
> +
> +struct zynq_flash_header {
> + uint32_t width_det;
> + uint32_t image_id;
> + uint32_t enc_stat;
> + uint32_t user;
> + uint32_t flash_offset;
> + uint32_t length;
> + uint32_t res0;
> + uint32_t start_of_exec;
> + uint32_t total_len;
> + uint32_t res1;
> + uint32_t checksum;
> + uint32_t res2;
> +};
Did you disagree with my suggestion last time around of merging the
flash_header and ps7reg_entry sections? At the very least, it seems
inconsistent that the zynq_reg_entrys have type __le32, and the members
of zynq_flash_header are uint32_t (even though they have the same
endianness requirement).
I still maintain you should move the REG macro currently in the board
flash_header.c here.
Josh
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