On Tue, Mar 19, 2013 at 10:21:57AM +0100, Steffen Trumtrar wrote:
> Add basic support for the Xilinx Zynq-7000 EPP architecture.
> The Zynq-7000 is an embedded processing platform that combines a Cortex A9
> dualcore MPSoC with an Artix-7 FPGA.
>
> Signed-off-by: Steffen Trumtrar <s.trumtrar@xxxxxxxxxxxxxx>
[..]
> +static int zynq_init(void)
> +{
> + u32 val;
> +
> + dsb();
> + isb();
> + writel(0xDF0D, ZYNQ_SLCR_UNLOCK);
> + /* remap ocm high */
> + writel(0x0000000F, 0xf8000910);
> + /* mpcore.filtering_start_address */
> + writel(0x00000000, 0xf8f00040);
> + /* mpcore.filtering_end_address */
> + writel(0xffe00000, 0xf8f00044);
> + val = readl(0xf8f00000);
> + val |= 0x2;
> + writel(val, 0xf8f00000);
> + dmb();
Doh! I should have read this before replying! This is what I was
looking for!
I think this will work nicely.
Josh
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