> > well NAND boot + nand rootfs works fine here (cpuimx25) and I assumeif your sd's partitions are detected by the kernel you must be able to
> > NAND boot + sd rootfs would work as sd is properly detected during boot.
> >
> > Yep, I believe it's more a question of me setting the parameters correctly
> upon boot. But without a proper low level init (which I don't have because
> I do not really understand all the details of the low level code), there
> are other factors which could inhibit the proper boot, as you mention below.
>
boot a rootfs on it it's just a bootargs problem (and kernel
configuration to have the right FS included).
That's my understanding too, however it does not work at the moment. But what's really important is that I have NOR support when loading barebox as first stage boot loader from SD card.
> I suppose WEIM configuration is done in the low level part, isn't it? Wherenothing prevents you from moving mxc_iomux_v3_setup_multiple_pads to
> would I find an appropriate example? I have been reading all the fsl
> board's low_level codes, but have a hard time figuring out how to apply it
> to my board.
>
> With regard to the IOMUX, I was under the impression that it does not
> matter much, since after low level code run, the execution path is:
>
> late_initcall()
> mem_initcall()
> device_initcall() --> add_cfi_flash_device()
> console_initcall() --> mxc_iomux_v3_setup_multiple_pads()
> core_initcall()
>
> So CFI/NOR detection happens before IOMUX setup, at least that's what I
> have gathered for my board copying from various other examples in barebox.
> What would the correct code execution path be from the architectural point
> of view?
>
device_initcall as done in
http://git.pengutronix.de/?p=barebox.git;a=blob;f=arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c;h=1b8f618138023b88893a024ddc0c078b7b9f2325;hb=c48de4beee21c3a5573cec084123c33ae08f6f7a
Thanks, I have done this now, looks much cleaner. Stil, I wonder about the order of things when powering and booting up the mx25 in general.
lowlevel -> AIPS -> MAX (MPR, SGPCR, MGPCR) -> M3IF -> MPLL clock -> other clocks
late_initcall -> fec_init
mem_initcall -> imx25_mem_init
device_initcall -> devices_init
console_initcall -> console_init
core_initcall -> core_setup
for the weim setting you may need to do something similar to what is
done on line 187 of :
http://git.pengutronix.de/?p=barebox.git;a=blob;f=arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c;h=63e87c9551c440edab572f5252a503ba4d533161;hb=c48de4beee21c3a5573cec084123c33ae08f6f7a
Now that piece certainly was missing, but how the heck did you find out those register values? Where did you get the information about writing to chip select 0 and selecting:
CSCR0U: 0x00008F03
CSCR0L: 0xA0330D01
CSCR0A: 0x002208C0
I have patched mx25-regs.h accordingly and added an equivalent call using the same register values:
diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h
index 73307c4..8225832 100644
--- a/arch/arm/mach-imx/include/mach/imx25-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx25-regs.h
@@ -72,6 +72,7 @@
#define CCM_LTR1 0x44
#define CCM_LTR2 0x48
#define CCM_LTR3 0x4c
+#define CCM_MCR 0x64
#define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9)
#define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12)
@@ -107,6 +108,22 @@
#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
+/* Chip Select Registers */
+#define IMX_WEIM_BASE WEIM_BASE
+#define CSxU(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x00) /* Chip Select x Upper Register */
+#define CSxL(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x04) /* Chip Select x Lower Register */
+#define CSxA(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x08) /* Chip Select x Addition Register */
+#define EIM __REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Register */
+
+#ifndef __ASSEMBLY__
+static inline void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned addional)
+{
+ CSxU(cs) = upper;
+ CSxL(cs) = lower;
+ CSxA(cs) = addional;
+}
+#endif /* __ASSEMBLY__ */
+
/*
* Definitions for the clocksource driver
*
But it still does not work. What could be missing? How can I find out more about which chip select I need? I'm practically married to the MX25-RM documentation, but still, it's one heck of a large piece of documentation. I found the following example (using cs2), but I am not sure this helps:
@; config WEIM to Async access with EDC, OEA, RWA, RWN, EBC, 16 bit port and PSR WRITE WEIM_CSCR2U, 0x12020802
WRITE WEIM_CSCR2L, 0x80330d03
@ ; config Flash to WRAP 8 mode (by half word accesses) WRITE_H (CS2_BASE_ADDR+0x2384), 0x60 @ ; offset = 0x11c2 << 1 for 16 bit port WRITE_H (CS2_BASE_ADDR+0x2384), 0x03
WRITE_H (CS2_BASE_ADDR+0x0), 0xff @ ; Flash to read mode
@ ; config to WEIM Sync access with WRAP8, 16 bit port WRITE WEIM_CSCR2U, 0x13510802
WRITE WEIM_CSCR2L, 0x80330d03
Could it be that I am missing an iomux setting? Clock missing? I am fairly certain that my NOR is at CS0, so the above example from the RM does not help much, I suppose.
Best regards
Roberto
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