Re: [PATCH 10] ARM: Add support for IXP4xx CPU and for Goramo Multilink router platform.

[Belisko Marek <marek.belisko@xxxxxxxxx>]

Hi,

On Tue, Dec 21, 2010 at 12:06 AM, Krzysztof Halasa <khc@xxxxxxxxx> wrote:
> Signed-off-by: Krzysztof HaÅasa <khc@xxxxxxxxx>
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 8cb86cb..56b5a0d 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -39,6 +39,13 @@ config ARCH_IMX
> Â Â Â Âbool "Freescale iMX-based"
> Â Â Â Âselect GENERIC_GPIO
>
> +config ARCH_IXP4XX
> + Â Â Â bool "Intel IXP4xx-based"
> + Â Â Â select CPU_32v5
> + Â Â Â select ARCH_SUPPORTS_BIG_ENDIAN
> + Â Â Â select CPU_BIG_ENDIAN
> + Â Â Â select ARCH_HAS_LOWLEVEL_INIT
> +
Should go to different Kconfig. This is ARM related and you have
intel cpu which is possibly x86.  Also in other patches you stick to ARM
but your CPU doesn't have ARM core.

> Âconfig ARCH_STM
> Â Â Â Âbool "SigmaTel/FSL iMX-based"
> Â Â Â Âselect GENERIC_GPIO
> @@ -67,6 +74,7 @@ source arch/arm/cpu/Kconfig
> Âsource arch/arm/mach-at91/Kconfig
> Âsource arch/arm/mach-ep93xx/Kconfig
> Âsource arch/arm/mach-imx/Kconfig
> +source arch/arm/mach-ixp4xx/Kconfig
> Âsource arch/arm/mach-stm/Kconfig
> Âsource arch/arm/mach-netx/Kconfig
> Âsource arch/arm/mach-nomadik/Kconfig
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 9729c23..2e9f99d 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -41,6 +41,7 @@ CPPFLAGS += $(CFLAGS_ABI) $(arch-y) $(tune-y)
> Âmachine-$(CONFIG_ARCH_AT91) Â Â Â Â Â Â:= at91
> Âmachine-$(CONFIG_ARCH_EP93XX) Â Â Â Â Â:= ep93xx
> Âmachine-$(CONFIG_ARCH_IMX) Â Â Â Â Â Â := imx
> +machine-$(CONFIG_ARCH_IXP4XX) Â Â Â Â Â:= ixp4xx
> Âmachine-$(CONFIG_ARCH_STM) Â Â Â Â Â Â := stm
> Âmachine-$(CONFIG_ARCH_NOMADIK) Â Â Â Â := nomadik
> Âmachine-$(CONFIG_ARCH_NETX) Â Â Â Â Â Â:= netx
> @@ -73,6 +74,7 @@ board-$(CONFIG_MACH_FREESCALE_MX35_3STACK) Â Â:= freescale-mx35-3-stack
> Âboard-$(CONFIG_MACH_IMX21ADS) Â Â Â Â Â Â Â Â Â:= imx21ads
> Âboard-$(CONFIG_MACH_IMX27ADS) Â Â Â Â Â Â Â Â Â:= imx27ads
> Âboard-$(CONFIG_MACH_MMCCPU) Â Â Â Â Â Â Â Â Â Â:= mmccpu
> +board-$(CONFIG_MACH_MULTILINK) Â Â Â Â Â Â Â Â := multilink
> Âboard-$(CONFIG_MACH_MX1ADS) Â Â Â Â Â Â Â Â Â Â:= mx1ads
> Âboard-$(CONFIG_MACH_NOMADIK_8815NHK) Â Â Â Â Â := nhk8815
> Âboard-$(CONFIG_MACH_NXDB500) Â Â Â Â Â Â Â Â Â := netx
> diff --git a/arch/arm/boards/multilink/Makefile b/arch/arm/boards/multilink/Makefile
> new file mode 100644
> index 0000000..d5a8bbc
> --- /dev/null
> +++ b/arch/arm/boards/multilink/Makefile
> @@ -0,0 +1 @@
> +obj-y += lowlevel_init.o multilink.o
> diff --git a/arch/arm/boards/multilink/config.h b/arch/arm/boards/multilink/config.h
> new file mode 100644
> index 0000000..e69de29
> diff --git a/arch/arm/boards/multilink/lowlevel_init.S b/arch/arm/boards/multilink/lowlevel_init.S
> new file mode 100644
> index 0000000..970ef72
> --- /dev/null
> +++ b/arch/arm/boards/multilink/lowlevel_init.S
> @@ -0,0 +1,64 @@
> +#include <mach/ixp4xx-regs.h>
> +
> + Â Â Â .section ".text_bare_init", "ax"
> + Â Â Â .balign 0x40
> + Â Â Â .space 0x40 /* configuration block at 0x40 */
> +
> + Â Â Â .macro DELAY_FOR cycles, reg0
> + Â Â Â ldr \reg0, =\cycles
> + Â Â Â subs \reg0, \reg0, #1
> + Â Â Â subne pc, pc, #0xc
> + Â Â Â .endm
> +
> +#define CFG_SDRAM_SIZE Â Â0x50 /* u32 */
> +#define CFG_SDRAM_CONF Â Â0x54 /* u32 */
> +#define CFG_SDRAM_MODE Â Â0x58 /* u32 */
> +#define CFG_SDRAM_REFRESH 0x5C /* u32 */
> +
> +.globl board_init_lowlevel
> +board_init_lowlevel:
> + Â Â Â mov r8, #IXP4XX_EXP_BASE(0)
> + Â Â Â ldr r1, [r8, #CFG_SDRAM_CONF]
> + Â Â Â ldr r2, =IXP4XX_SDRAM_CONFIG
> + Â Â Â str r1, [r2]
> +
> + Â Â Â /* disable refresh cycles */
> + Â Â Â mov r1, #0
> + Â Â Â add r2, r2, #4 /* r2 = IXP4XX_SDRAM_REFRESH */
> + Â Â Â str r1, [r2]
> +
> + Â Â Â /* send NOP command */
> + Â Â Â mov r1, #3
> + Â Â Â add r3, r2, #4 /* r3 = IXP4XX_SDRAM_IR */
> + Â Â Â str r1, [r3]
> + Â Â Â DELAY_FOR 0x4000, r0
> +
> + Â Â Â /* set SDRAM internal refresh */
> + Â Â Â ldr r1, [r8, #CFG_SDRAM_REFRESH]
> + Â Â Â str r1, [r2]
> + Â Â Â DELAY_FOR 0x4000, r0
> +
> + Â Â Â /* send precharge-all command to close all open banks */
> + Â Â Â mov r1, #2
> + Â Â Â str r1, [r3]
> + Â Â Â DELAY_FOR 0x4000, r0
> +
> + Â Â Â /* provide 8 auto-refresh cycles */
> + Â Â Â mov r1, #4
> + Â Â Â mov r4, #8
> +1: Â Â str r1, [r3]
> + Â Â Â DELAY_FOR 0x100, r0
> + Â Â Â subs r4, r4, #1
> + Â Â Â bne 1b
> +
> + Â Â Â /* set mode register in SDRAM */
> + Â Â Â ldr r1, [r8, #CFG_SDRAM_MODE]
> + Â Â Â str r1, [r3]
> + Â Â Â DELAY_FOR 0x4000, r0
> +
> + Â Â Â /* send normal operation command */
> + Â Â Â mov r1, #6
> + Â Â Â str r1, [r3]
> + Â Â Â DELAY_FOR 0x4000, r0
> +
> + Â Â Â mov pc, lr
> diff --git a/arch/arm/boards/multilink/multilink.c b/arch/arm/boards/multilink/multilink.c
> new file mode 100644
> index 0000000..f2fb8f4
> --- /dev/null
> +++ b/arch/arm/boards/multilink/multilink.c
> @@ -0,0 +1,144 @@
> +//#define DEBUG
> +#include <common.h>
> +#include <errno.h>
> +#include <init.h>
> +#include <linux/types.h>
> +#include <asm/armlinux.h>
> +#include <asm/io.h>
> +#include <generated/mach-types.h>
> +#include <mach/ixp4xx-regs.h>
> +#include <mach/platform.h>
> +
> +/* offsets from start of flash ROM = 0x50000000 */
> +#define CFG_ETH0_ADDRESS Â Â 0x40 /* 6 bytes */
> +#define CFG_ETH1_ADDRESS Â Â 0x46 /* 6 bytes */
> +#define CFG_REV Â Â Â Â Â Â Â0x4C /* u32 */
> +#define CFG_SDRAM_SIZE Â Â Â 0x50 /* u32 */
> +#define CFG_SDRAM_CONF Â Â Â 0x54 /* u32 */
> +#define CFG_SDRAM_MODE Â Â Â 0x58 /* u32 */
> +#define CFG_SDRAM_REFRESH Â Â0x5C /* u32 */
> +
> +#define CFG_HW_BITS Â Â Â Â Â0x60 /* u32 */
> +#define ÂCFG_HW_USB_PORTS Â Â0x00000007 /* 0 = no NEC chip, 1-5 = ports # */
> +#define ÂCFG_HW_HAS_PCI_SLOT 0x00000008
> +#define ÂCFG_HW_HAS_ETH0 Â Â 0x00000010
> +#define ÂCFG_HW_HAS_ETH1 Â Â 0x00000020
> +#define ÂCFG_HW_HAS_HSS0 Â Â 0x00000040
> +#define ÂCFG_HW_HAS_HSS1 Â Â 0x00000080
> +#define ÂCFG_HW_HAS_UART0 Â Â0x00000100
> +#define ÂCFG_HW_HAS_UART1 Â Â0x00000200
> +#define ÂCFG_HW_HAS_EEPROM Â 0x00000400
> +
> +#define ETH_ALEN Â Â Â Â Â Â 6
> +
> +#define BAREBOX_START Â Â Â Â0x00000
> +#define BAREBOX_LENGTH Â Â Â 0x34000
> +#define NPE_A_START Â Â Â Â Â(BAREBOX_START + BAREBOX_LENGTH)
> +#define NPE_A_LENGTH Â Â Â Â 0x05000
> +#define NPE_B_START Â Â Â Â Â(NPE_A_START + NPE_A_LENGTH)
> +#define NPE_B_LENGTH Â Â Â Â 0x03000
> +#define NPE_C_START Â Â Â Â Â(NPE_B_START + NPE_B_LENGTH)
> +#define NPE_C_LENGTH Â Â Â Â 0x04000
> +#define NPE_ENV0_START Â Â Â (NPE_C_START + NPE_C_LENGTH)
> +#define NPE_ENV0_LENGTH Â Â Â0x20000
> +
> +static struct device_d cfi_dev = {
> +    .name   = "cfi_flash",
> + Â Â Â .map_base = IXP4XX_EXP_BASE(0),
> +    .size   = 16 * 1024 * 1024,
> +};
> +
> +static struct eth_plat_info eth_pinfo[2] = {
> + Â Â Â {
> +        .regs   = IXP4XX_EthB_BASE,
> +        .npe   Â= 1,
> +        .phy   Â= 0,
> +        .rxq   Â= 20,
> + Â Â Â Â Â Â Â .txreadyq = 29,
> + Â Â Â }, {
> +        .regs   = IXP4XX_EthC_BASE,
> +        .npe   Â= 2,
> +        .phy   Â= 1,
> +        .rxq   Â= 21,
> + Â Â Â Â Â Â Â .txreadyq = 30,
> + Â Â Â }
> +};
> +
> +static struct device_d eth_dev[2] = {
> + Â Â Â {
> +        .name      = "ixp4xx_eth",
> + Â Â Â Â Â Â Â .platform_data Â= &eth_pinfo[0],
> + Â Â Â }, {
> +        .id       = 1,
> +        .name      = "ixp4xx_eth",
> + Â Â Â Â Â Â Â .platform_data Â= &eth_pinfo[1],
> + Â Â Â }
> +};
> +
> +static struct memory_platform_data ram_pdata = {
> +    .name      = "ram0",
> +    .flags     Â= DEVFS_RDWR,
> +};
> +
> +struct device_d sdram_dev = {
> +    .id       = -1,
> +    .name      = "mem",
> +    .map_base    = 0x00000000,
> +    .size      = 32 * 1024 * 1024,
> + Â Â Â .platform_data Â= &ram_pdata,
> +};
> +
> +static inline u8 __init flash_readb(u32 addr)
> +{
> + Â Â Â return __raw_readb(IXP4XX_EXP_BASE(0) + addr);
> +}
> +
> +static int __init gml_devices_init(void)
> +{
> + Â Â Â u32 hw_bits;
> + Â Â Â int i;
> +
> + Â Â Â IXP4XX_EXP_CS0 = IXP4XX_EXP_EN | IXP4XX_EXP_INTEL |
> + Â Â Â Â Â Â Â IXP4XX_EXP_BITS(24) | IXP4XX_EXP_WR_EN | IXP4XX_EXP_BYTE_RD16;
> + Â Â Â i = register_device(&cfi_dev);
> + Â Â Â if (i)
> + Â Â Â Â Â Â Â goto out;
> +
> + Â Â Â devfs_add_partition("nor0", BAREBOX_START, BAREBOX_LENGTH,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â DEVFS_PARTITION_FIXED | DEVFS_PARTITION_READONLY, "barebox");
> + Â Â Â devfs_add_partition("nor0", NPE_A_START, NPE_A_LENGTH,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â DEVFS_PARTITION_FIXED | DEVFS_PARTITION_READONLY, "NPE-A");
> + Â Â Â devfs_add_partition("nor0", NPE_B_START, NPE_B_LENGTH,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â DEVFS_PARTITION_FIXED | DEVFS_PARTITION_READONLY, "NPE-B");
> + Â Â Â devfs_add_partition("nor0", NPE_C_START, NPE_C_LENGTH,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â DEVFS_PARTITION_FIXED | DEVFS_PARTITION_READONLY, "NPE-C");
> + Â Â Â devfs_add_partition("nor0", NPE_ENV0_START, NPE_ENV0_LENGTH,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â DEVFS_PARTITION_FIXED, "env0");
> +
> + Â Â Â hw_bits = __raw_readl(IXP4XX_EXP_BASE(0) + CFG_HW_BITS);
> +
> + Â Â Â if (hw_bits & CFG_HW_HAS_ETH0) {
> + Â Â Â Â Â Â Â for (i = 0; i < ETH_ALEN; i++)
> + Â Â Â Â Â Â Â Â Â Â Â eth_pinfo[0].hwaddr[i] = flash_readb(CFG_ETH0_ADDRESS + i);
> + Â Â Â Â Â Â Â register_device(&eth_dev[0]);
> + Â Â Â }
> +
> + Â Â Â if (hw_bits & CFG_HW_HAS_ETH1) {
> + Â Â Â Â Â Â Â for (i = 0; i < ETH_ALEN; i++)
> + Â Â Â Â Â Â Â Â Â Â Â eth_pinfo[1].hwaddr[i] = flash_readb(CFG_ETH1_ADDRESS + i);
> + Â Â Â Â Â Â Â register_device(&eth_dev[1]);
> + Â Â Â }
> +
> + Â Â Â sdram_dev.size = __raw_readl(IXP4XX_EXP_BASE(0) + CFG_SDRAM_SIZE);
> + Â Â Â i = register_device(&sdram_dev);
> + Â Â Â if (i)
> + Â Â Â Â Â Â Â goto out;
> +
> + Â Â Â armlinux_add_dram(&sdram_dev);
> + Â Â Â armlinux_set_bootparams((void *)(0x00000100));
> + Â Â Â armlinux_set_architecture(MACH_TYPE_GORAMO_MLR);
> +
> +out:
> + Â Â Â return i;
> +}
> +device_initcall(gml_devices_init);
> diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
> new file mode 100644
> index 0000000..f5e4b41
> --- /dev/null
> +++ b/arch/arm/mach-ixp4xx/Kconfig
> @@ -0,0 +1,26 @@
> +if ARCH_IXP4XX
> +
> +choice
> + Â Â Â prompt "IXP4xx Board Type"
> +
> +config MACH_MULTILINK
> + Â Â Â bool "Goramo MultiLink"
> + Â Â Â select MACH_HAS_LOWLEVEL_INIT
> +endchoice
> +
> +config BOARDINFO
> + Â Â Â default "Goramo MultiLink" if MACH_MULTILINK
> +
> +config IXP4XX_QMGR
> + Â Â Â tristate "IXP4xx Queue Manager support"
> + Â Â Â help
> + Â Â Â Â This driver supports IXP4xx built-in hardware queue manager
> + Â Â Â Â and is required by the Ethernet driver.
> +
> +config IXP4XX_NPE
> + Â Â Â tristate "IXP4xx Network Processor Engine support"
> + Â Â Â help
> + Â Â Â Â This driver supports IXP4xx built-in network coprocessors
> + Â Â Â Â and is required by the Ethernet driver.
> +
> +endif
> diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
> new file mode 100644
> index 0000000..aa38991
> --- /dev/null
> +++ b/arch/arm/mach-ixp4xx/Makefile
> @@ -0,0 +1,3 @@
> +obj-y += lowlevel_init.o generic.o
> +obj-$(CONFIG_IXP4XX_QMGR) += qmgr.o
> +obj-$(CONFIG_IXP4XX_NPE) += npe.o
> diff --git a/arch/arm/mach-ixp4xx/generic.c b/arch/arm/mach-ixp4xx/generic.c
> new file mode 100644
> index 0000000..02394a4
> --- /dev/null
> +++ b/arch/arm/mach-ixp4xx/generic.c
> @@ -0,0 +1,120 @@
> +#include <common.h>
> +#include <init.h>
> +#include <ns16550.h>
> +#include <asm/armlinux.h>
> +#include <asm/io.h>
> +#include <mach/ixp4xx-regs.h>
> +
> +#define OSTS_FREQUENCY 66666000
> +
> +void reset_cpu(ulong addr)
> +{
> + Â Â Â /* Use on-chip reset capability */
> + Â Â Â /* This may not work on IXP425 rev. A0 */
> +
> + Â Â Â IXP4XX_OSWK = IXP4XX_WDT_KEY;
> + Â Â Â IXP4XX_OSWT = 0; /* request immediate reset */
> + Â Â Â IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
> + Â Â Â while (1)
> + Â Â Â Â Â Â Â ;
> +}
> +
> +#include <clock.h>
> +
> +/**
> + * @brief Provide a simple clock read
> + *
> + * Nothing is simpler.. read direct from clock and provide it
> + * to the caller.
> + *
> + * @return clock counter
> + */
> +static uint64_t ixp4xx_clocksource_read(void)
> +{
> + Â Â Â return IXP4XX_OSTS;
> +}
> +
> +static struct clocksource cs = {
> + Â Â Â .read = ixp4xx_clocksource_read,
> + Â Â Â .mask = 0xffffffff,
> + Â Â Â .shift = 10,
> +};
> +
> +/**
> + * @brief Initialize the Clock
> + *
> + * We use the Time-Stamp Timer
> + *
> + * @return result of @ref init_clock
> + */
> +static int ixp4xx_clocksource_init(void)
> +{
> + Â Â Â cs.mult = clocksource_hz2mult(OSTS_FREQUENCY, cs.shift);
> +
> + Â Â Â return init_clock(&cs);
> +}
> +
> +/* Run me at boot time */
> +core_initcall(ixp4xx_clocksource_init);
> +
> +
> +#ifdef CONFIG_DRIVER_SERIAL_NS16550
> +
> +/**
> + * @brief UART port register read function for IXP4XX
> + *
> + * @param base base address of UART
> + * @param reg_idx register index
> + *
> + * @return character read from register
> + */
> +unsigned int ixp4xx_uart_read(unsigned long base, unsigned char reg_idx)
> +{
> + Â Â Â return readb(4 * reg_idx + 3 /* big-endian */ + (uint8_t *)base);
> +}
> +EXPORT_SYMBOL(ixp4xx_uart_read);
> +
> +/**
> + * @brief UART port register write function for IXP4XX
> + *
> + * @param val value to write
> + * @param base base address of UART
> + * @param reg_idx register index
> + *
> + * @return void
> + */
> +void ixp4xx_uart_write(unsigned int val, unsigned long base, unsigned char reg_idx)
> +{
> + Â Â Â writeb(val, 4 * reg_idx + 3 /* big-endian */ + (uint8_t *)base);
> +}
> +EXPORT_SYMBOL(ixp4xx_uart_write);
> +
> +
> +static struct NS16550_plat serial_plat = {
> + Â Â Â .clock = 14745600,
> + Â Â Â .f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
> + Â Â Â .reg_read = ixp4xx_uart_read,
> + Â Â Â .reg_write = ixp4xx_uart_write,
> +};
> +
> +static struct device_d ixp4xx_serial_device = {
> + Â Â Â .name = "serial_ns16550",
> + Â Â Â .map_base = (u32)IXP4XX_UART1_BASE,
> + Â Â Â .size = 1024,
> + Â Â Â .platform_data = (void *)&serial_plat,
> +};
> +
> +/**
> + * @brief UART serial port initialization
> + *
> + * @return result of device registration
> + */
> +static int ixp4xx_console_init(void)
> +{
> + Â Â Â /* Register the serial port */
> + Â Â Â return register_device(&ixp4xx_serial_device);
> +}
> +
> +console_initcall(ixp4xx_console_init);
> +
> +#endif /* CONFIG_DRIVER_SERIAL_NS16550 */
> diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h
> new file mode 100644
> index 0000000..3de021e
> --- /dev/null
> +++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h
> @@ -0,0 +1,70 @@
> +/*
> + * arch/arm/mach-ixp4xx/include/mach/cpu.h
> + *
> + * IXP4XX cpu type detection
> + *
> + * Copyright (C) 2007 MontaVista Software, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#ifndef __ASM_ARCH_CPU_H__
> +#define __ASM_ARCH_CPU_H__
> +
> +#include <linux/types.h>
> +
> +/* Processor id value in CP15 Register 0 */
> +#define IXP42X_PROCESSOR_ID_VALUE 0x690541c0 /* including unused 0x690541Ex */
> +#define IXP42X_PROCESSOR_ID_MASK Â0xffffffc0
> +
> +#define IXP43X_PROCESSOR_ID_VALUE 0x69054040
> +#define IXP43X_PROCESSOR_ID_MASK Â0xfffffff0
> +
> +#define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */
> +#define IXP46X_PROCESSOR_ID_MASK Â0xfffffff0
> +
> +#define cpu_is_ixp42x_rev_a0() ((read_cpuid_id() & (IXP42X_PROCESSOR_ID_MASK | 0xF)) == \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â IXP42X_PROCESSOR_ID_VALUE)
> +#define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \
> + Â Â Â Â Â Â Â Â Â Â Â ÂIXP42X_PROCESSOR_ID_VALUE)
> +#define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \
> + Â Â Â Â Â Â Â Â Â Â Â ÂIXP43X_PROCESSOR_ID_VALUE)
> +#define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \
> + Â Â Â Â Â Â Â Â Â Â Â ÂIXP46X_PROCESSOR_ID_VALUE)
> +
> +/*
> + * The CPU ID never changes at run time, so we might as well tell the
> + * compiler that it's constant. ÂUse this function to read the CPU ID
> + * rather than directly reading processor_id or read_cpuid() directly.
> + */
> +static inline u32 __attribute_const__ read_cpuid_id(void)
> +{
> + Â Â Â u32 val;
> + Â Â Â asm("mrc p15, 0, %0, c0, c0, 0" : "=r" (val) : : "cc");
> +
> + Â Â Â return val;
> +}
> +
> +static inline u32 ixp4xx_read_feature_bits(void)
> +{
> + Â Â Â u32 val = ~IXP4XX_EXP_CFG2;
> +
> + Â Â Â if (cpu_is_ixp42x_rev_a0())
> + Â Â Â Â Â Â Â return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_AES);
> + Â Â Â if (cpu_is_ixp42x())
> + Â Â Â Â Â Â Â return val & IXP42X_FEATURE_MASK;
> + Â Â Â if (cpu_is_ixp43x())
> + Â Â Â Â Â Â Â return val & IXP43X_FEATURE_MASK;
> + Â Â Â return val & IXP46X_FEATURE_MASK;
> +}
> +
> +static inline void ixp4xx_write_feature_bits(u32 value)
> +{
> + Â Â Â IXP4XX_EXP_CFG2 = ~value;
> +}
> +
> +#endif Â/* _ASM_ARCH_CPU_H */
> diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
> new file mode 100644
> index 0000000..da4dc8a
> --- /dev/null
> +++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
> @@ -0,0 +1,365 @@
> +/*
> + * Register definitions for IXP4xx chipset.
> + *
> + * Copyright (C) 2002 Intel Corporation.
> + * Copyright (C) 2003-2004 MontaVista Software, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#ifndef _ASM_ARM_IXP4XX_H_
> +#define _ASM_ARM_IXP4XX_H_
> +
> +#ifdef __ASSEMBLER__
> +#define IXP4XX_REG(reg) Â(reg)
> +#else
> +#define IXP4XX_REG(reg) Â(*(volatile u32 *)(reg))
> +#define IXP4XX_BASE(reg) ((u32*)(reg))
> +#endif
> +
> +/* Expansion Bus region */
> +
> +/* Queue Manager */
> +#define IXP4XX_QMGR_BASE Â Â Â Â Â Â Â(0x60000000)
> +#define IXP4XX_QMGR_REGION_SIZE Â Â Â (0x00004000)
> +
> +
> +/* PCI Config registers */
> +#define IXP4XX_PCI_CFG_BASE Â Â Â Â Â (0xC0000000)
> +#define IXP4XX_PCI_CFG_REGION_SIZE Â Â(0x00001000)
> +
> +/* Peripheral space */
> +#define IXP4XX_PERIPHERAL_BASE Â Â Â Â(0xC8000000)
> +#define IXP4XX_PERIPHERAL_REGION_SIZE (0x00013000)
> +
> +/*
> + * Debug UART
> + *
> + * This is basically a remap of UART1 into a region that is section
> + * aligned so that it can be used with the low-level debug code.
> + */
> +#define IXP4XX_DEBUG_UART_BASE Â Â Â Â(0xC8000000)
> +#define IXP4XX_DEBUG_UART_REGION_SIZE (0x00001000)
> +
> +/* Expansion Bus Controller registers. */
> +#define IXP4XX_EXP_CS0 Â Â Â IXP4XX_REG(0xC4000000)
> +#define IXP4XX_EXP_CS1 Â Â Â IXP4XX_REG(0xC4000004)
> +#define IXP4XX_EXP_CS2 Â Â Â IXP4XX_REG(0xC4000008)
> +#define IXP4XX_EXP_CS3 Â Â Â IXP4XX_REG(0xC400000C)
> +#define IXP4XX_EXP_CS4 Â Â Â IXP4XX_REG(0xC4000010)
> +#define IXP4XX_EXP_CS5 Â Â Â IXP4XX_REG(0xC4000014)
> +#define IXP4XX_EXP_CS6 Â Â Â IXP4XX_REG(0xC4000018)
> +#define IXP4XX_EXP_CS7 Â Â Â IXP4XX_REG(0xC400001C)
> +
> +#define IXP4XX_EXP_BASE(n) Â(0x50000000 + (n) * 1000000)
> +
> +#define IXP4XX_EXP_EN Â Â Â Â0x80000000
> +#define IXP4XX_EXP_T1(n) Â Â(0x10000000 * (n)) /* valid: 0 - 3 */
> +#define IXP4XX_EXP_T2(n) Â Â(0x04000000 * (n)) /* valid: 0 - 3 */
> +#define IXP4XX_EXP_T3(n) Â Â(0x00400000 * (n)) /* valid: 0 - 15 */
> +#define IXP4XX_EXP_T4(n) Â Â(0x00100000 * (n)) /* valid: 0 - 3 */
> +#define IXP4XX_EXP_T5(n) Â Â(0x00010000 * (n)) /* valid: 0 - 15 */
> +#define IXP4XX_EXP_INTEL Â Â 0x00000000
> +#define IXP4XX_EXP_MOTO Â Â Â0x00004000
> +#define IXP4XX_EXP_HPI Â Â Â 0x00008000
> +#define IXP4XX_EXP_BITS(n) Â(0x00000400 * ((n) - 9)) /* valid: 9 - 24 */
> +#define IXP4XX_EXP_BYTE_RD16 0x00000040
> +#define IXP4XX_EXP_HRDY_POL Â0x00000020
> +#define IXP4XX_EXP_MUX_EN Â Â0x00000010
> +#define IXP4XX_EXP_SPLT_EN Â 0x00000008
> +#define IXP4XX_EXP_WR_EN Â Â 0x00000002
> +#define IXP4XX_EXP_BYTE_EN Â 0x00000001
> +
> +#define IXP4XX_EXP_CFG0 Â Â ÂIXP4XX_REG(0xC4000020)
> +#define IXP4XX_EXP_CFG1 Â Â ÂIXP4XX_REG(0xC4000024)
> +#define IXP4XX_EXP_CFG2 Â Â ÂIXP4XX_REG(0xC4000028)
> +#define IXP4XX_EXP_CFG3 Â Â ÂIXP4XX_REG(0xC400002C)
> +
> +
> +/* Peripheral Space Register Region Base Addresses */
> +#define IXP4XX_UART1_BASE Â ÂIXP4XX_BASE(IXP4XX_PERIPHERAL_BASE + 0x0000)
> +#define IXP4XX_UART2_BASE Â ÂIXP4XX_BASE(IXP4XX_PERIPHERAL_BASE + 0x1000)
> +#define IXP4XX_PMU_BASE Â Â ÂIXP4XX_BASE(IXP4XX_PERIPHERAL_BASE + 0x2000)
> +#define IXP4XX_INTC_BASE Â Â IXP4XX_BASE(IXP4XX_PERIPHERAL_BASE + 0x3000)
> +#define IXP4XX_GPIO_BASE Â Â IXP4XX_BASE(IXP4XX_PERIPHERAL_BASE + 0x4000)
> +#define IXP4XX_NPEA_BASE Â Â IXP4XX_BASE(IXP4XX_PERIPHERAL_BASE + 0x6000)
> +#define IXP4XX_NPEB_BASE Â Â IXP4XX_BASE(IXP4XX_PERIPHERAL_BASE + 0x7000)
> +#define IXP4XX_NPEC_BASE Â Â IXP4XX_BASE(IXP4XX_PERIPHERAL_BASE + 0x8000)
> +#define IXP4XX_EthB_BASE Â Â IXP4XX_BASE(IXP4XX_PERIPHERAL_BASE + 0x9000)
> +#define IXP4XX_EthC_BASE Â Â IXP4XX_BASE(IXP4XX_PERIPHERAL_BASE + 0xA000)
> +#define IXP4XX_USB_BASE Â Â ÂIXP4XX_BASE(IXP4XX_PERIPHERAL_BASE + 0xB000)
> +/* IXP46x only */
> +#define IXP4XX_EthA_BASE Â Â IXP4XX_BASE(IXP4XX_PERIPHERAL_BASE + 0xC000)
> +#define IXP4XX_EthB1_BASE Â ÂIXP4XX_BASE(IXP4XX_PERIPHERAL_BASE + 0xD000)
> +#define IXP4XX_EthB2_BASE Â ÂIXP4XX_BASE(IXP4XX_PERIPHERAL_BASE + 0xE000)
> +#define IXP4XX_EthB3_BASE Â ÂIXP4XX_BASE(IXP4XX_PERIPHERAL_BASE + 0xF000)
> +#define IXP4XX_TIMESYNC_BASE IXP4XX_BASE(IXP4XX_PERIPHERAL_BASE + 0x10000)
> +#define IXP4XX_I2C_BASE Â Â ÂIXP4XX_BASE(IXP4XX_PERIPHERAL_BASE + 0x11000)
> +#define IXP4XX_SSP_BASE Â Â ÂIXP4XX_BASE(IXP4XX_PERIPHERAL_BASE + 0x12000)
> +
> +/*
> + ÂConstants to make it easy to access Interrupt Controller registers
> + */
> +#define IXP4XX_ICPR_OFFSET Â 0x00 /* Interrupt Status */
> +#define IXP4XX_ICMR_OFFSET Â 0x04 /* Interrupt Enable */
> +#define IXP4XX_ICLR_OFFSET Â 0x08 /* Interrupt IRQ/FIQ Select */
> +#define IXP4XX_ICIP_OFFSET Â 0x0C /* IRQ Status */
> +#define IXP4XX_ICFP_OFFSET Â 0x10 /* FIQ Status */
> +#define IXP4XX_ICHR_OFFSET Â 0x14 /* Interrupt Priority */
> +#define IXP4XX_ICIH_OFFSET Â 0x18 /* IRQ Highest Pri Int */
> +#define IXP4XX_ICFH_OFFSET Â 0x1C /* FIQ Highest Pri Int */
> +
> +/* IXP465-only */
> +#define IXP4XX_ICPR2_OFFSET Â0x20 /* Interrupt Status 2 */
> +#define IXP4XX_ICMR2_OFFSET Â0x24 /* Interrupt Enable 2 */
> +#define IXP4XX_ICLR2_OFFSET Â0x28 /* Interrupt IRQ/FIQ Select 2 */
> +#define IXP4XX_ICIP2_OFFSET Â0x2C /* IRQ Status */
> +#define IXP4XX_ICFP2_OFFSET Â0x30 /* FIQ Status */
> +#define IXP4XX_ICEEN_OFFSET Â0x34 /* Error High Pri Enable */
> +
> +
> +/* Interrupt Controller Register Definitions. */
> +#define IXP4XX_INTC_REG(x) Â ((volatile u32 *)(IXP4XX_INTC_BASE + (x)))
> +
> +#define IXP4XX_ICPR Â Â Â Â ÂIXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET)
> +#define IXP4XX_ICMR Â Â Â Â ÂIXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET)
> +#define IXP4XX_ICLR Â Â Â Â ÂIXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET)
> +#define IXP4XX_ICIP Â Â Â Â ÂIXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET)
> +#define IXP4XX_ICFP Â Â Â Â ÂIXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET)
> +#define IXP4XX_ICHR Â Â Â Â ÂIXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)
> +#define IXP4XX_ICIH Â Â Â Â ÂIXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET)
> +#define IXP4XX_ICFH Â Â Â Â ÂIXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)
> +#define IXP4XX_ICPR2 Â Â Â Â IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET)
> +#define IXP4XX_ICMR2 Â Â Â Â IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET)
> +#define IXP4XX_ICLR2 Â Â Â Â IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET)
> +#define IXP4XX_ICIP2 Â Â Â Â IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET)
> +#define IXP4XX_ICFP2 Â Â Â Â IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET)
> +#define IXP4XX_ICEEN Â Â Â Â IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET)
> +
> +/* Constants to make it easy to access GPIO registers */
> +#define IXP4XX_GPIO_GPOUTR_OFFSET Â 0x00
> +#define IXP4XX_GPIO_GPOER_OFFSET Â Â0x04
> +#define IXP4XX_GPIO_GPINR_OFFSET Â Â0x08
> +#define IXP4XX_GPIO_GPISR_OFFSET Â Â0x0C
> +#define IXP4XX_GPIO_GPIT1R_OFFSET Â 0x10
> +#define IXP4XX_GPIO_GPIT2R_OFFSET Â 0x14
> +#define IXP4XX_GPIO_GPCLKR_OFFSET Â 0x18
> +#define IXP4XX_GPIO_GPDBSELR_OFFSET 0x1C
> +
> +/* GPIO Register Definitions - perform only 32-bit reads/writes */
> +#define IXP4XX_GPIO_REG(x) Â ((volatile u32 *)(IXP4XX_GPIO_BASE + (x)))
> +
> +#define IXP4XX_GPIO_GPOUTR Â IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET)
> +#define IXP4XX_GPIO_GPOER Â ÂIXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET)
> +#define IXP4XX_GPIO_GPINR Â ÂIXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET)
> +#define IXP4XX_GPIO_GPISR Â ÂIXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET)
> +#define IXP4XX_GPIO_GPIT1R Â IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET)
> +#define IXP4XX_GPIO_GPIT2R Â IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET)
> +#define IXP4XX_GPIO_GPCLKR Â IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET)
> +#define IXP4XX_GPIO_GPDBSELR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET)
> +
> +/* GPIO register bit definitions */
> +
> +/* Interrupt styles */
> +#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH Â0x0
> +#define IXP4XX_GPIO_STYLE_ACTIVE_LOW Â 0x1
> +#define IXP4XX_GPIO_STYLE_RISING_EDGE Â0x2
> +#define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3
> +#define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4
> +
> +/* Mask used to clear interrupt styles */
> +#define IXP4XX_GPIO_STYLE_CLEAR Â Â Â Â0x7
> +#define IXP4XX_GPIO_STYLE_SIZE Â Â Â Â 3
> +
> +/* Operating System Timer Register Definitions. */
> +#define IXP4XX_OSTS Â Â Â Â ÂIXP4XX_REG(0xC8005000) /* Continious TimeStamp */
> +#define IXP4XX_OST1 Â Â Â Â ÂIXP4XX_REG(0xC8005004) /* Timer 1 Timestamp */
> +#define IXP4XX_OSRT1 Â Â Â Â IXP4XX_REG(0xC8005008) /* Timer 1 Reload */
> +#define IXP4XX_OST2 Â Â Â Â ÂIXP4XX_REG(0xC800500C) /* Timer 2 Timestamp */
> +#define IXP4XX_OSRT2 Â Â Â Â IXP4XX_REG(0xC8005010) /* Timer 2 Reload */
> +#define IXP4XX_OSWT Â Â Â Â ÂIXP4XX_REG(0xC8005014) /* Watchdog Timer */
> +#define IXP4XX_OSWE Â Â Â Â ÂIXP4XX_REG(0xC8005018) /* Watchdog Enable */
> +#define IXP4XX_OSWK Â Â Â Â ÂIXP4XX_REG(0xC800501C) /* Watchdog Key */
> +#define IXP4XX_OSST Â Â Â Â ÂIXP4XX_REG(0xC8005020) /* Timer Status */
> +
> +/* Timer register values and bit definitions */
> +#define IXP4XX_OST_ENABLE Â Â Â Â Â Â0x00000001
> +#define IXP4XX_OST_ONE_SHOT Â Â Â Â Â0x00000002
> +/* Low order bits of reload value ignored */
> +#define IXP4XX_OST_RELOAD_MASK Â Â Â 0x00000003
> +#define IXP4XX_OST_DISABLED Â Â Â Â Â0x00000000
> +#define IXP4XX_OSST_TIMER_1_PEND Â Â 0x00000001
> +#define IXP4XX_OSST_TIMER_2_PEND Â Â 0x00000002
> +#define IXP4XX_OSST_TIMER_TS_PEND Â Â0x00000004
> +#define IXP4XX_OSST_TIMER_WDOG_PEND Â0x00000008
> +#define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
> +
> +#define IXP4XX_WDT_KEY Â Â Â Â Â Â Â 0x0000482E
> +
> +#define IXP4XX_WDT_RESET_ENABLE Â Â Â0x00000001
> +#define IXP4XX_WDT_IRQ_ENABLE Â Â Â Â0x00000002
> +#define IXP4XX_WDT_COUNT_ENABLE Â Â Â0x00000004
> +
> +
> +/* Constants to make it easy to access PCI Control/Status registers */
> +#define PCI_NP_AD_OFFSET Â Â Â Â Â 0x00
> +#define PCI_NP_CBE_OFFSET Â Â Â Â Â0x04
> +#define PCI_NP_WDATA_OFFSET Â Â Â Â0x08
> +#define PCI_NP_RDATA_OFFSET Â Â Â Â0x0c
> +#define PCI_CRP_AD_CBE_OFFSET Â Â Â0x10
> +#define PCI_CRP_WDATA_OFFSET Â Â Â 0x14
> +#define PCI_CRP_RDATA_OFFSET Â Â Â 0x18
> +#define PCI_CSR_OFFSET Â Â Â Â Â Â 0x1c
> +#define PCI_ISR_OFFSET Â Â Â Â Â Â 0x20
> +#define PCI_INTEN_OFFSET Â Â Â Â Â 0x24
> +#define PCI_DMACTRL_OFFSET Â Â Â Â 0x28
> +#define PCI_AHBMEMBASE_OFFSET Â Â Â0x2c
> +#define PCI_AHBIOBASE_OFFSET Â Â Â 0x30
> +#define PCI_PCIMEMBASE_OFFSET Â Â Â0x34
> +#define PCI_AHBDOORBELL_OFFSET Â Â 0x38
> +#define PCI_PCIDOORBELL_OFFSET Â Â 0x3C
> +#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
> +#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
> +#define PCI_ATPDMA0_LENADDR_OFFSET 0x48
> +#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
> +#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
> +#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
> +
> +/* PCI Control/Status Registers */
> +#define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE + (x)))
> +
> +#define PCI_NP_AD Â Â Â Â Â ÂIXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
> +#define PCI_NP_CBE Â Â Â Â Â IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
> +#define PCI_NP_WDATA Â Â Â Â IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
> +#define PCI_NP_RDATA Â Â Â Â IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
> +#define PCI_CRP_AD_CBE Â Â Â IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
> +#define PCI_CRP_WDATA Â Â Â ÂIXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
> +#define PCI_CRP_RDATA Â Â Â ÂIXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
> +#define PCI_CSR Â Â Â Â Â Â ÂIXP4XX_PCI_CSR(PCI_CSR_OFFSET)
> +#define PCI_ISR Â Â Â Â Â Â ÂIXP4XX_PCI_CSR(PCI_ISR_OFFSET)
> +#define PCI_INTEN Â Â Â Â Â ÂIXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
> +#define PCI_DMACTRL Â Â Â Â ÂIXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
> +#define PCI_AHBMEMBASE Â Â Â IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
> +#define PCI_AHBIOBASE Â Â Â ÂIXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
> +#define PCI_PCIMEMBASE Â Â Â IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
> +#define PCI_AHBDOORBELL Â Â ÂIXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
> +#define PCI_PCIDOORBELL Â Â ÂIXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
> +#define PCI_ATPDMA0_AHBADDR ÂIXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
> +#define PCI_ATPDMA0_PCIADDR ÂIXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
> +#define PCI_ATPDMA0_LENADDR ÂIXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
> +#define PCI_ATPDMA1_AHBADDR ÂIXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
> +#define PCI_ATPDMA1_PCIADDR ÂIXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
> +#define PCI_ATPDMA1_LENADDR ÂIXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
> +
> +/* PCI register values and bit definitions */
> +
> +/* CSR bit definitions */
> +#define PCI_CSR_HOST Â Â Â Â 0x00000001
> +#define PCI_CSR_ARBEN Â Â Â Â0x00000002
> +#define PCI_CSR_ADS Â Â Â Â Â0x00000004
> +#define PCI_CSR_PDS Â Â Â Â Â0x00000008
> +#define PCI_CSR_ABE Â Â Â Â Â0x00000010
> +#define PCI_CSR_DBT Â Â Â Â Â0x00000020
> +#define PCI_CSR_ASE Â Â Â Â Â0x00000100
> +#define PCI_CSR_IC Â Â Â Â Â 0x00008000
> +
> +/* ISR (Interrupt status) Register bit definitions */
> +#define PCI_ISR_PSE Â Â Â Â Â0x00000001
> +#define PCI_ISR_PFE Â Â Â Â Â0x00000002
> +#define PCI_ISR_PPE Â Â Â Â Â0x00000004
> +#define PCI_ISR_AHBE Â Â Â Â 0x00000008
> +#define PCI_ISR_APDC Â Â Â Â 0x00000010
> +#define PCI_ISR_PADC Â Â Â Â 0x00000020
> +#define PCI_ISR_ADB Â Â Â Â Â0x00000040
> +#define PCI_ISR_PDB Â Â Â Â Â0x00000080
> +
> +/* INTEN (Interrupt Enable) Register bit definitions */
> +#define PCI_INTEN_PSE Â Â Â Â0x00000001
> +#define PCI_INTEN_PFE Â Â Â Â0x00000002
> +#define PCI_INTEN_PPE Â Â Â Â0x00000004
> +#define PCI_INTEN_AHBE Â Â Â 0x00000008
> +#define PCI_INTEN_APDC Â Â Â 0x00000010
> +#define PCI_INTEN_PADC Â Â Â 0x00000020
> +#define PCI_INTEN_ADB Â Â Â Â0x00000040
> +#define PCI_INTEN_PDB Â Â Â Â0x00000080
> +
> +/* Shift value for byte enable on NP cmd/byte enable register */
> +#define IXP4XX_PCI_NP_CBE_BESL 4
> +
> +/* PCI commands supported by NP access unit */
> +#define NP_CMD_IOREAD Â Â Â Â0x2
> +#define NP_CMD_IOWRITE Â Â Â 0x3
> +#define NP_CMD_CONFIGREAD Â Â0xA
> +#define NP_CMD_CONFIGWRITE Â 0xB
> +#define NP_CMD_MEMREAD Â Â Â 0x6
> +#define NP_CMD_MEMWRITE Â Â Â0x7
> +
> +/* Constants for CRP access into local config space */
> +#define CRP_AD_CBE_BESL Â Â Â20
> +#define CRP_AD_CBE_WRITE Â Â 0x00010000
> +
> +/* USB Device Controller */
> +# define IXP4XX_USB_REG(x) Â (*((volatile u32 *)(x)))
> +
> +/* SDRAM Controller registers. */
> +#define IXP4XX_SDRAM_CONFIG ÂIXP4XX_REG(0xCC000000)
> +#define IXP4XX_SDRAM_REFRESH IXP4XX_REG(0xCC000004)
> +#define IXP4XX_SDRAM_IR Â Â ÂIXP4XX_REG(0xCC000008)
> +
> +/* "fuse" bits of IXP_EXP_CFG2 */
> +/* All IXP4xx CPUs */
> +#define IXP4XX_FEATURE_RCOMP Â Â Â Â Â Â(1 << 0)
> +#define IXP4XX_FEATURE_USB_DEVICE Â Â Â (1 << 1)
> +#define IXP4XX_FEATURE_HASH Â Â Â Â Â Â (1 << 2)
> +#define IXP4XX_FEATURE_AES Â Â Â Â Â Â Â(1 << 3)
> +#define IXP4XX_FEATURE_DES Â Â Â Â Â Â Â(1 << 4)
> +#define IXP4XX_FEATURE_HDLC Â Â Â Â Â Â (1 << 5)
> +#define IXP4XX_FEATURE_AAL Â Â Â Â Â Â Â(1 << 6)
> +#define IXP4XX_FEATURE_HSS Â Â Â Â Â Â Â(1 << 7)
> +#define IXP4XX_FEATURE_UTOPIA Â Â Â Â Â (1 << 8)
> +#define IXP4XX_FEATURE_NPEB_ETH0 Â Â Â Â(1 << 9)
> +#define IXP4XX_FEATURE_NPEC_ETH Â Â Â Â (1 << 10)
> +#define IXP4XX_FEATURE_RESET_NPEA Â Â Â (1 << 11)
> +#define IXP4XX_FEATURE_RESET_NPEB Â Â Â (1 << 12)
> +#define IXP4XX_FEATURE_RESET_NPEC Â Â Â (1 << 13)
> +#define IXP4XX_FEATURE_PCI Â Â Â Â Â Â Â(1 << 14)
> +#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
> +#define IXP4XX_FEATURE_XSCALE_MAX_FREQ Â(3 << 22)
> +#define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP Â Â Â Â Â Â| \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_USB_DEVICE Â Â Â | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_HASH Â Â Â Â Â Â | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_AES Â Â Â Â Â Â Â| \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_DES Â Â Â Â Â Â Â| \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_HDLC Â Â Â Â Â Â | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_AAL Â Â Â Â Â Â Â| \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_HSS Â Â Â Â Â Â Â| \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_UTOPIA Â Â Â Â Â | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_NPEB_ETH0 Â Â Â Â| \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_NPEC_ETH Â Â Â Â | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_RESET_NPEA Â Â Â | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_RESET_NPEB Â Â Â | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_RESET_NPEC Â Â Â | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_PCI Â Â Â Â Â Â Â| \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_XSCALE_MAX_FREQ)
> +
> +/* IXP43x/46x CPUs */
> +#define IXP4XX_FEATURE_ECC_TIMESYNC Â Â (1 << 15)
> +#define IXP4XX_FEATURE_USB_HOST Â Â Â Â (1 << 18)
> +#define IXP4XX_FEATURE_NPEA_ETH Â Â Â Â (1 << 19)
> +#define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK Â Â Â Â Â Â | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_ECC_TIMESYNC Â Â | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_USB_HOST Â Â Â Â | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_NPEA_ETH)
> +
> +/* IXP46x CPU (including IXP455) only */
> +#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 Â(1 << 20)
> +#define IXP4XX_FEATURE_RSA Â Â Â Â Â Â Â(1 << 21)
> +#define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK Â Â Â Â Â Â | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_NPEB_ETH_1_TO_3 Â| \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â ÂIXP4XX_FEATURE_RSA)
> +
> +#endif
> diff --git a/arch/arm/mach-ixp4xx/include/mach/npe.h b/arch/arm/mach-ixp4xx/include/mach/npe.h
> new file mode 100644
> index 0000000..18bd01b
> --- /dev/null
> +++ b/arch/arm/mach-ixp4xx/include/mach/npe.h
> @@ -0,0 +1,30 @@
> +#ifndef __IXP4XX_NPE_H
> +#define __IXP4XX_NPE_H
> +
> +#include <common.h>
> +
> +#define NPE_NAME_LENGTH 5
> +
> +struct npe_regs {
> + Â Â Â u32 exec_addr, exec_data, exec_status_cmd, exec_count;
> + Â Â Â u32 action_points[4];
> + Â Â Â u32 watchpoint_fifo, watch_count;
> + Â Â Â u32 profile_count;
> + Â Â Â u32 messaging_status, messaging_control;
> + Â Â Â u32 mailbox_status, /*messaging_*/ in_out_fifo;
> +};
> +
> +struct npe {
> + Â Â Â struct npe_regs *regs;
> + Â Â Â int id, valid;
> + Â Â Â const char name[NPE_NAME_LENGTH + 1];
> +};
> +
> +int npe_running(struct npe *npe);
> +int npe_send_message(struct npe *npe, const void *msg, const char *what);
> +int npe_recv_message(struct npe *npe, void *msg, const char *what);
> +int npe_send_recv_message(struct npe *npe, void *msg, const char *what);
> +int npe_load_firmware(struct npe *npe);
> +struct npe *npe_request(int id);
> +
> +#endif /* __IXP4XX_NPE_H */
> diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
> new file mode 100644
> index 0000000..1df4aa4
> --- /dev/null
> +++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
> @@ -0,0 +1,15 @@
> +#include <asm/types.h>
> +
> +#define IXP4XX_ETH_NPEA 0x00
> +#define IXP4XX_ETH_NPEB 0x10
> +#define IXP4XX_ETH_NPEC 0x20
> +
> +/* Information about built-in Ethernet MAC interfaces */
> +struct eth_plat_info {
> + Â Â Â void *regs;
> + Â Â Â u8 npe;
> + Â Â Â u8 phy; /* MII PHY ID, 0 - 31 */
> + Â Â Â u8 rxq; /* configurable, currently 0 - 31 only */
> + Â Â Â u8 txreadyq;
> + Â Â Â u8 hwaddr[6];
> +};
> diff --git a/arch/arm/mach-ixp4xx/include/mach/qmgr.h b/arch/arm/mach-ixp4xx/include/mach/qmgr.h
> new file mode 100644
> index 0000000..4e9b8d4
> --- /dev/null
> +++ b/arch/arm/mach-ixp4xx/include/mach/qmgr.h
> @@ -0,0 +1,164 @@
> +/*
> + * Copyright (C) 2007 Krzysztof Halasa <khc@xxxxxxxxx>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of version 2 of the GNU General Public License
> + * as published by the Free Software Foundation.
> + */
> +
> +#ifndef IXP4XX_QMGR_H
> +#define IXP4XX_QMGR_H
> +
> +#include <common.h>
> +#include <mach/ixp4xx-regs.h>
> +#include <asm/io.h>
> +
> +#define DEBUG_QMGR Â Â Â 0
> +
> +#define HALF_QUEUES Â Â 32
> +#define QUEUES Â Â Â Â Â64
> +#define MAX_QUEUE_LENGTH 4 /* in dwords */
> +
> +#define QUEUE_STAT1_EMPTY Â Â Â Â Â Â Â 1 /* queue status bits */
> +#define QUEUE_STAT1_NEARLY_EMPTY Â Â Â Â2
> +#define QUEUE_STAT1_NEARLY_FULL Â Â Â Â 4
> +#define QUEUE_STAT1_FULL Â Â Â Â Â Â Â Â8
> +#define QUEUE_STAT2_UNDERFLOW Â Â Â Â Â 1
> +#define QUEUE_STAT2_OVERFLOW Â Â Â Â Â Â2
> +
> +#define QUEUE_WATERMARK_0_ENTRIES Â Â Â 0
> +#define QUEUE_WATERMARK_1_ENTRY Â Â Â Â 1
> +#define QUEUE_WATERMARK_2_ENTRIES Â Â Â 2
> +#define QUEUE_WATERMARK_4_ENTRIES Â Â Â 3
> +#define QUEUE_WATERMARK_8_ENTRIES Â Â Â 4
> +#define QUEUE_WATERMARK_16_ENTRIES Â Â Â5
> +#define QUEUE_WATERMARK_32_ENTRIES Â Â Â6
> +#define QUEUE_WATERMARK_64_ENTRIES Â Â Â7
> +
> +/* queue interrupt request conditions */
> +#define QUEUE_IRQ_SRC_EMPTY Â Â Â Â Â Â 0
> +#define QUEUE_IRQ_SRC_NEARLY_EMPTY Â Â Â1
> +#define QUEUE_IRQ_SRC_NEARLY_FULL Â Â Â 2
> +#define QUEUE_IRQ_SRC_FULL Â Â Â Â Â Â Â3
> +#define QUEUE_IRQ_SRC_NOT_EMPTY Â Â Â Â 4
> +#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY Â5
> +#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL Â 6
> +#define QUEUE_IRQ_SRC_NOT_FULL Â Â Â Â Â7
> +
> +struct qmgr_regs {
> + Â Â Â u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
> + Â Â Â u32 stat1[4]; Â Â Â Â /* 0x400 - 0x40F */
> + Â Â Â u32 stat2[2]; Â Â Â Â /* 0x410 - 0x417 */
> + Â Â Â u32 statne_h; Â Â Â Â /* 0x418 - queue nearly empty */
> + Â Â Â u32 statf_h; Â Â Â Â Â/* 0x41C - queue full */
> + Â Â Â u32 irqsrc[4]; Â Â Â Â/* 0x420 - 0x42F IRC source */
> + Â Â Â u32 irqen[2]; Â Â Â Â /* 0x430 - 0x437 IRQ enabled */
> + Â Â Â u32 irqstat[2]; Â Â Â /* 0x438 - 0x43F - IRQ access only */
> + Â Â Â u32 reserved[1776];
> + Â Â Â u32 sram[2048]; Â Â Â /* 0x2000 - 0x3FFF - config and buffer */
> +};
> +
> +static const struct qmgr_regs *qmgr_regs = (struct qmgr_regs *)IXP4XX_QMGR_BASE;
> +
> +void qmgr_set_irq(unsigned int queue, int src,
> + Â Â Â Â Â Â Â Â void (*handler)(void *pdev), void *pdev);
> +void qmgr_enable_irq(unsigned int queue);
> +void qmgr_disable_irq(unsigned int queue);
> +
> +/* request_ and release_queue() must be called from non-IRQ context */
> +
> +#if DEBUG_QMGR
> +extern char qmgr_queue_descs[HALF_QUEUES][32];
> +
> +void qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
> + Â Â Â Â Â Â Â Â Â Â Â unsigned int nearly_empty_watermark,
> + Â Â Â Â Â Â Â Â Â Â Â unsigned int nearly_full_watermark,
> + Â Â Â Â Â Â Â Â Â Â Â const char *desc_format, const char* name);
> +#else
> +void __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
> + Â Â Â Â Â Â Â Â Â Â Â Â unsigned int nearly_empty_watermark,
> + Â Â Â Â Â Â Â Â Â Â Â Â unsigned int nearly_full_watermark);
> +#define qmgr_request_queue(queue, len, nearly_empty_watermark, Â Â Â \
> + Â Â Â Â Â Â Â Â Â Â Â Â Ânearly_full_watermark, desc_format, name) \
> + Â Â Â __qmgr_request_queue(queue, len, nearly_empty_watermark, Â Â \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Ânearly_full_watermark)
> +#endif
> +
> +void qmgr_release_queue(unsigned int queue);
> +
> +
> +static inline void qmgr_put_entry(unsigned int queue, u32 val)
> +{
> +#if DEBUG_QMGR
> + Â Â Â BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
> +
> + Â Â Â fprintf(stderr, "Queue %s(%i) put %X\n",
> + Â Â Â Â Â Â Â qmgr_queue_descs[queue], queue, val);
> +#endif
> + Â Â Â __raw_writel(val, &qmgr_regs->acc[queue][0]);
> +}
> +
> +static inline u32 qmgr_get_entry(unsigned int queue)
> +{
> + Â Â Â u32 val;
> + Â Â Â val = __raw_readl(&qmgr_regs->acc[queue][0]);
> +#if DEBUG_QMGR
> + Â Â Â BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
> +
> + Â Â Â fprintf(stderr, "Queue %s(%i) get %X\n",
> + Â Â Â Â Â Â Â qmgr_queue_descs[queue], queue, val);
> +#endif
> + Â Â Â return val;
> +}
> +
> +static inline int __qmgr_get_stat1(unsigned int queue)
> +{
> + Â Â Â return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
> + Â Â Â Â Â Â Â >> ((queue & 7) << 2)) & 0xF;
> +}
> +
> +/**
> + * qmgr_stat_empty() - checks if a hardware queue is empty
> + * @queue: queue number
> + *
> + * Returns non-zero value if the queue is empty.
> + */
> +static inline int qmgr_stat_empty(unsigned int queue)
> +{
> + Â Â Â return __qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY;
> +}
> +
> +/**
> + * qmgr_stat_below_low_watermark() - checks if a queue is below low watermark
> + * @queue: queue number
> + *
> + * Returns non-zero value if the queue is below low watermark.
> + */
> +static inline int qmgr_stat_below_low_watermark(unsigned int queue)
> +{
> + Â Â Â return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY;
> +}
> +
> +/**
> + * qmgr_stat_above_high_watermark() - checks if a queue is above high watermark
> + * @queue: queue number
> + *
> + * Returns non-zero value if the queue is above high watermark
> + */
> +static inline int qmgr_stat_above_high_watermark(unsigned int queue)
> +{
> + Â Â Â return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL;
> +}
> +
> +/**
> + * qmgr_stat_full() - checks if a hardware queue is full
> + * @queue: queue number
> + *
> + * Returns non-zero value if the queue is full.
> + */
> +static inline int qmgr_stat_full(unsigned int queue)
> +{
> + Â Â Â return __qmgr_get_stat1(queue) & QUEUE_STAT1_FULL;
> +}
> +
> +#endif
> diff --git a/arch/arm/mach-ixp4xx/lowlevel_init.S b/arch/arm/mach-ixp4xx/lowlevel_init.S
> new file mode 100644
> index 0000000..a4e93ef
> --- /dev/null
> +++ b/arch/arm/mach-ixp4xx/lowlevel_init.S
> @@ -0,0 +1,17 @@
> +#include <mach/ixp4xx-regs.h>
> +
> + Â Â Â .section ".text_bare_init", "ax"
> +
> + Â Â Â .globl arch_init_lowlevel
> +arch_init_lowlevel:
> + Â Â Â ldr r0, cfg
> + Â Â Â ldr r1, [r0]
> + Â Â Â and r1, r1, #~0x80000000 /* unmap EXP bus from 0x0 */
> + Â Â Â str r1, [r0]
> +
> + Â Â Â /* return to ROM */
> + Â Â Â orr lr, #0x50000000
> + Â Â Â mov pc, lr
> +
> +cfg:
> + Â Â Â .word IXP4XX_EXP_CFG0
> diff --git a/arch/arm/mach-ixp4xx/npe.c b/arch/arm/mach-ixp4xx/npe.c
> new file mode 100644
> index 0000000..a8ddd5a
> --- /dev/null
> +++ b/arch/arm/mach-ixp4xx/npe.c
> @@ -0,0 +1,668 @@
> +/*
> + * Intel IXP4xx Network Processor Engine driver for Linux
> + *
> + * Copyright (C) 2007 Krzysztof Halasa <khc@xxxxxxxxx>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of version 2 of the GNU General Public License
> + * as published by the Free Software Foundation.
> + */
> +
> +#include <common.h>
> +#include <errno.h>
> +#include <fs.h>
> +#include <init.h>
> +#include <malloc.h>
> +#include <asm/byteorder.h>
> +#include <asm/io.h>
> +#include <mach/ixp4xx-regs.h>
> +#include <mach/cpu.h>
> +#include <mach/npe.h>
> +
> +#define DEBUG_MSG Â Â Â Â Â Â Â Â Â Â Â0
> +#define DEBUG_FW Â Â Â Â Â Â Â Â Â Â Â 0
> +
> +#define NPE_COUNT Â Â Â Â Â Â Â Â Â Â Â3
> +#define MAX_RETRIES Â Â Â Â Â Â Â Â Â Â1000 Â/* microseconds */
> +#define NPE_42X_DATA_SIZE Â Â Â Â Â Â Â0x800 /* in dwords */
> +#define NPE_46X_DATA_SIZE Â Â Â Â Â Â Â0x1000
> +#define NPE_A_42X_INSTR_SIZE Â Â Â Â Â 0x1000
> +#define NPE_B_AND_C_42X_INSTR_SIZE Â Â 0x800
> +#define NPE_46X_INSTR_SIZE Â Â Â Â Â Â 0x1000
> +#define REGS_SIZE Â Â Â Â Â Â Â Â Â Â Â0x1000
> +
> +#define NPE_PHYS_REG Â Â Â Â Â Â Â Â Â 32
> +
> +#define FW_MAGIC Â Â Â Â Â Â Â Â Â Â Â 0xFEEDF00D
> +#define FW_BLOCK_TYPE_INSTR Â Â Â Â Â Â0x0
> +#define FW_BLOCK_TYPE_DATA Â Â Â Â Â Â 0x1
> +#define FW_BLOCK_TYPE_EOF Â Â Â Â Â Â Â0xF
> +
> +/* NPE exec status (read) and command (write) */
> +#define CMD_NPE_STEP Â Â Â Â Â Â Â Â Â 0x01
> +#define CMD_NPE_START Â Â Â Â Â Â Â Â Â0x02
> +#define CMD_NPE_STOP Â Â Â Â Â Â Â Â Â 0x03
> +#define CMD_NPE_CLR_PIPE Â Â Â Â Â Â Â 0x04
> +#define CMD_CLR_PROFILE_CNT Â Â Â Â Â Â0x0C
> +#define CMD_RD_INS_MEM Â Â Â Â Â Â Â Â 0x10 /* instruction memory */
> +#define CMD_WR_INS_MEM Â Â Â Â Â Â Â Â 0x11
> +#define CMD_RD_DATA_MEM Â Â Â Â Â Â Â Â0x12 /* data memory */
> +#define CMD_WR_DATA_MEM Â Â Â Â Â Â Â Â0x13
> +#define CMD_RD_ECS_REG Â Â Â Â Â Â Â Â 0x14 /* exec access register */
> +#define CMD_WR_ECS_REG Â Â Â Â Â Â Â Â 0x15
> +
> +#define STAT_RUN Â Â Â Â Â Â Â Â Â Â Â 0x80000000
> +#define STAT_STOP Â Â Â Â Â Â Â Â Â Â Â0x40000000
> +#define STAT_CLEAR Â Â Â Â Â Â Â Â Â Â 0x20000000
> +#define STAT_ECS_K Â Â Â Â Â Â Â Â Â Â 0x00800000 /* pipeline clean */
> +
> +#define NPE_STEVT Â Â Â Â Â Â Â Â Â Â Â0x1B
> +#define NPE_STARTPC Â Â Â Â Â Â Â Â Â Â0x1C
> +#define NPE_REGMAP Â Â Â Â Â Â Â Â Â Â 0x1E
> +#define NPE_CINDEX Â Â Â Â Â Â Â Â Â Â 0x1F
> +
> +#define INSTR_WR_REG_SHORT Â Â Â Â Â Â 0x0000C000
> +#define INSTR_WR_REG_BYTE Â Â Â Â Â Â Â0x00004000
> +#define INSTR_RD_FIFO Â Â Â Â Â Â Â Â Â0x0F888220
> +#define INSTR_RESET_MBOX Â Â Â Â Â Â Â 0x0FAC8210
> +
> +#define ECS_BG_CTXT_REG_0 Â Â Â Â Â Â Â0x00 /* Background Executing Context */
> +#define ECS_BG_CTXT_REG_1 Â Â Â Â Â Â Â0x01 /* Stack level */
> +#define ECS_BG_CTXT_REG_2 Â Â Â Â Â Â Â0x02
> +#define ECS_PRI_1_CTXT_REG_0 Â Â Â Â Â 0x04 /* Priority 1 Executing Context */
> +#define ECS_PRI_1_CTXT_REG_1 Â Â Â Â Â 0x05 /* Stack level */
> +#define ECS_PRI_1_CTXT_REG_2 Â Â Â Â Â 0x06
> +#define ECS_PRI_2_CTXT_REG_0 Â Â Â Â Â 0x08 /* Priority 2 Executing Context */
> +#define ECS_PRI_2_CTXT_REG_1 Â Â Â Â Â 0x09 /* Stack level */
> +#define ECS_PRI_2_CTXT_REG_2 Â Â Â Â Â 0x0A
> +#define ECS_DBG_CTXT_REG_0 Â Â Â Â Â Â 0x0C /* Debug Executing Context */
> +#define ECS_DBG_CTXT_REG_1 Â Â Â Â Â Â 0x0D /* Stack level */
> +#define ECS_DBG_CTXT_REG_2 Â Â Â Â Â Â 0x0E
> +#define ECS_INSTRUCT_REG Â Â Â Â Â Â Â 0x11 /* NPE Instruction Register */
> +
> +#define ECS_REG_0_ACTIVE Â Â Â Â Â Â Â 0x80000000 /* all levels */
> +#define ECS_REG_0_NEXTPC_MASK Â Â Â Â Â0x1FFF0000 /* BG/PRI1/PRI2 levels */
> +#define ECS_REG_0_LDUR_BITS Â Â Â Â Â Â8
> +#define ECS_REG_0_LDUR_MASK Â Â Â Â Â Â0x00000700 /* all levels */
> +#define ECS_REG_1_CCTXT_BITS Â Â Â Â Â 16
> +#define ECS_REG_1_CCTXT_MASK Â Â Â Â Â 0x000F0000 /* all levels */
> +#define ECS_REG_1_SELCTXT_BITS Â Â Â Â 0
> +#define ECS_REG_1_SELCTXT_MASK Â Â Â Â 0x0000000F /* all levels */
> +#define ECS_DBG_REG_2_IF Â Â Â Â Â Â Â 0x00100000 /* debug level */
> +#define ECS_DBG_REG_2_IE Â Â Â Â Â Â Â 0x00080000 /* debug level */
> +
> +/* NPE watchpoint_fifo register bit */
> +#define WFIFO_VALID Â Â Â Â Â Â Â Â Â Â0x80000000
> +
> +/* NPE messaging_status register bit definitions */
> +#define MSGSTAT_OFNE Â0x00010000 /* OutFifoNotEmpty */
> +#define MSGSTAT_IFNF Â0x00020000 /* InFifoNotFull */
> +#define MSGSTAT_OFNF Â0x00040000 /* OutFifoNotFull */
> +#define MSGSTAT_IFNE Â0x00080000 /* InFifoNotEmpty */
> +#define MSGSTAT_MBINT 0x00100000 /* Mailbox interrupt */
> +#define MSGSTAT_IFINT 0x00200000 /* InFifo interrupt */
> +#define MSGSTAT_OFINT 0x00400000 /* OutFifo interrupt */
> +#define MSGSTAT_WFINT 0x00800000 /* WatchFifo interrupt */
> +
> +/* NPE messaging_control register bit definitions */
> +#define MSGCTL_OUT_FIFO Â Â Â 0x00010000 /* enable output FIFO */
> +#define MSGCTL_IN_FIFO Â Â Â Â0x00020000 /* enable input FIFO */
> +#define MSGCTL_OUT_FIFO_WRITE 0x01000000 /* enable FIFO + WRITE */
> +#define MSGCTL_IN_FIFO_WRITE Â0x02000000
> +
> +/* NPE mailbox_status value for reset */
> +#define RESET_MBOX_STAT Â Â Â Â Â0x0000F0F0
> +
> +#define print_npe(npe, fmt, ...) fprintf(stderr, "%s: " fmt, npe->name, ## __VA_ARGS__)
> +
> +#if DEBUG_MSG
> +#define debug_msg(npe, fmt, ...) print_npe(npe, fmt, ## __VA_ARGS__)
> +#else
> +#define debug_msg(npe, fmt, ...)
> +#endif
> +
> +static struct {
> + Â Â Â u32 reg, val;
> +} ecs_reset[] = {
> + Â Â Â {ECS_BG_CTXT_REG_0, Â Â0xA0000000},
> + Â Â Â {ECS_BG_CTXT_REG_1, Â Â0x01000000},
> + Â Â Â {ECS_BG_CTXT_REG_2, Â Â0x00008000},
> + Â Â Â {ECS_PRI_1_CTXT_REG_0, 0x20000080},
> + Â Â Â {ECS_PRI_1_CTXT_REG_1, 0x01000000},
> + Â Â Â {ECS_PRI_1_CTXT_REG_2, 0x00008000},
> + Â Â Â {ECS_PRI_2_CTXT_REG_0, 0x20000080},
> + Â Â Â {ECS_PRI_2_CTXT_REG_1, 0x01000000},
> + Â Â Â {ECS_PRI_2_CTXT_REG_2, 0x00008000},
> + Â Â Â {ECS_DBG_CTXT_REG_0, Â 0x20000000},
> + Â Â Â {ECS_DBG_CTXT_REG_1, Â 0x00000000},
> + Â Â Â {ECS_DBG_CTXT_REG_2, Â 0x001E0000},
> + Â Â Â {ECS_INSTRUCT_REG, Â Â 0x1003C00F},
> +};
> +
> +static struct npe npe_tab[NPE_COUNT] = {
> + Â Â Â {
> + Â Â Â Â Â Â Â .regs = (struct npe_regs *)IXP4XX_NPEA_BASE,
> + Â Â Â Â Â Â Â .id = 0,
> + Â Â Â Â Â Â Â .name = "NPE-A",
> + Â Â Â }, {
> + Â Â Â Â Â Â Â .regs = (struct npe_regs *)IXP4XX_NPEB_BASE,
> + Â Â Â Â Â Â Â .id = 1,
> + Â Â Â Â Â Â Â .name = "NPE-B",
> + Â Â Â }, {
> + Â Â Â Â Â Â Â .regs = (struct npe_regs *)IXP4XX_NPEC_BASE,
> + Â Â Â Â Â Â Â .id = 2,
> + Â Â Â Â Â Â Â .name = "NPE-C",
> + Â Â Â }
> +};
> +
> +int npe_running(struct npe *npe)
> +{
> + Â Â Â return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0;
> +}
> +
> +static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data)
> +{
> + Â Â Â __raw_writel(data, &npe->regs->exec_data);
> + Â Â Â __raw_writel(addr, &npe->regs->exec_addr);
> + Â Â Â __raw_writel(cmd, &npe->regs->exec_status_cmd);
> +}
> +
> +static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd)
> +{
> + Â Â Â __raw_writel(addr, &npe->regs->exec_addr);
> + Â Â Â __raw_writel(cmd, &npe->regs->exec_status_cmd);
> + Â Â Â /* Iintroduce extra read cycles after issuing read command to NPE
> + Â Â Â Â Âso that we read the register after the NPE has updated it.
> + Â Â Â Â ÂThis is to overcome race condition between XScale and NPE */
> + Â Â Â __raw_readl(&npe->regs->exec_data);
> + Â Â Â __raw_readl(&npe->regs->exec_data);
> + Â Â Â return __raw_readl(&npe->regs->exec_data);
> +}
> +
> +static void npe_clear_active(struct npe *npe, u32 reg)
> +{
> + Â Â Â u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG);
> + Â Â Â npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE);
> +}
> +
> +static void npe_start(struct npe *npe)
> +{
> + Â Â Â /* ensure only Background Context Stack Level is active */
> + Â Â Â npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0);
> + Â Â Â npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0);
> + Â Â Â npe_clear_active(npe, ECS_DBG_CTXT_REG_0);
> +
> + Â Â Â __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
> + Â Â Â __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd);
> +}
> +
> +static void npe_stop(struct npe *npe)
> +{
> + Â Â Â __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd);
> + Â Â Â __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/
> +}
> +
> +static int npe_debug_instr(struct npe *npe, u32 instr, u32 ctx, u32 ldur)
> +{
> + Â Â Â u32 wc;
> + Â Â Â int i;
> +
> + Â Â Â /* set the Active bit, and the LDUR, in the debug level */
> + Â Â Â npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG,
> + Â Â Â Â Â Â Â Â Â Â ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS));
> +
> + Â Â Â /* set CCTXT at ECS DEBUG L3 to specify in which context to execute
> + Â Â Â Â Âthe instruction, and set SELCTXT at ECS DEBUG Level to specify
> + Â Â Â Â Âwhich context store to access.
> + Â Â Â Â ÂDebug ECS Level Reg 1 has form 0x000n000n, where n = context number
> + Â Â Â */
> + Â Â Â npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG,
> + Â Â Â Â Â Â Â Â Â Â (ctx << ECS_REG_1_CCTXT_BITS) |
> + Â Â Â Â Â Â Â Â Â Â (ctx << ECS_REG_1_SELCTXT_BITS));
> +
> + Â Â Â /* clear the pipeline */
> + Â Â Â __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
> +
> + Â Â Â /* load NPE instruction into the instruction register */
> + Â Â Â npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr);
> +
> + Â Â Â /* we need this value later to wait for completion of NPE execution
> + Â Â Â Â Âstep */
> + Â Â Â wc = __raw_readl(&npe->regs->watch_count);
> +
> + Â Â Â /* issue a Step One command via the Execution Control register */
> + Â Â Â __raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd);
> +
> + Â Â Â /* Watch Count register increments when NPE completes an instruction */
> + Â Â Â for (i = 0; i < MAX_RETRIES; i++) {
> + Â Â Â Â Â Â Â if (wc != __raw_readl(&npe->regs->watch_count))
> + Â Â Â Â Â Â Â Â Â Â Â return 0;
> + Â Â Â Â Â Â Â udelay(1);
> + Â Â Â }
> +
> + Â Â Â print_npe(npe, "reset: npe_debug_instr(): timeout\n");
> + Â Â Â return -ETIMEDOUT;
> +}
> +
> +static int npe_logical_reg_write8(struct npe *npe, u32 addr, u8 val, u32 ctx)
> +{
> + Â Â Â /* here we build the NPE assembler instruction: mov8 d0, #0 */
> + Â Â Â u32 instr = INSTR_WR_REG_BYTE | /* OpCode */
> + Â Â Â Â Â Â Â addr << 9 | Â Â Â Â Â Â /* base Operand */
> + Â Â Â Â Â Â Â (val & 0x1F) << 4 | Â Â /* lower 5 bits to immediate data */
> + Â Â Â Â Â Â Â (val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */
> + Â Â Â return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
> +}
> +
> +static int npe_logical_reg_write16(struct npe *npe, u32 addr, u16 val, u32 ctx)
> +{
> + Â Â Â /* here we build the NPE assembler instruction: mov16 d0, #0 */
> + Â Â Â u32 instr = INSTR_WR_REG_SHORT | /* OpCode */
> + Â Â Â Â Â Â Â addr << 9 | Â Â Â Â Â Â /* base Operand */
> + Â Â Â Â Â Â Â (val & 0x1F) << 4 | Â Â /* lower 5 bits to immediate data */
> + Â Â Â Â Â Â Â (val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */
> + Â Â Â return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
> +}
> +
> +static int npe_logical_reg_write32(struct npe *npe, u32 addr, u32 val, u32 ctx)
> +{
> + Â Â Â /* write in 16 bit steps first the high and then the low value */
> + Â Â Â if (npe_logical_reg_write16(npe, addr, val >> 16, ctx))
> + Â Â Â Â Â Â Â return -ETIMEDOUT;
> + Â Â Â return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx);
> +}
> +
> +static int npe_reset(struct npe *npe)
> +{
> + Â Â Â u32 val, ctl, exec_count, ctx_reg2;
> + Â Â Â int i;
> +
> + Â Â Â ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) &
> + Â Â Â Â Â Â Â 0x3F3FFFFF;
> +
> + Â Â Â /* disable parity interrupt */
> + Â Â Â __raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control);
> +
> + Â Â Â /* pre exec - debug instruction */
> + Â Â Â /* turn off the halt bit by clearing Execution Count register. */
> + Â Â Â exec_count = __raw_readl(&npe->regs->exec_count);
> + Â Â Â __raw_writel(0, &npe->regs->exec_count);
> + Â Â Â /* ensure that IF and IE are on (temporarily), so that we don't end up
> + Â Â Â Â Âstepping forever */
> + Â Â Â ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG);
> + Â Â Â npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 |
> + Â Â Â Â Â Â Â Â Â Â ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE);
> +
> + Â Â Â /* clear the FIFOs */
> + Â Â Â while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID)
> + Â Â Â Â Â Â Â ;
> + Â Â Â while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE)
> + Â Â Â Â Â Â Â /* read from the outFIFO until empty */
> + Â Â Â Â Â Â Â print_npe(npe, "npe_reset: read FIFO = 0x%X\n",
> + Â Â Â Â Â Â Â Â Â Â Â Â __raw_readl(&npe->regs->in_out_fifo));
> +
> + Â Â Â while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)
> + Â Â Â Â Â Â Â /* step execution of the NPE intruction to read inFIFO using
> + Â Â Â Â Â Â Â Â Âthe Debug Executing Context stack */
> + Â Â Â Â Â Â Â if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0))
> + Â Â Â Â Â Â Â Â Â Â Â return -ETIMEDOUT;
> +
> + Â Â Â /* reset the mailbox reg from the XScale side */
> + Â Â Â __raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status);
> + Â Â Â /* from NPE side */
> + Â Â Â if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0))
> + Â Â Â Â Â Â Â return -ETIMEDOUT;
> +
> + Â Â Â /* Reset the physical registers in the NPE register file */
> + Â Â Â for (val = 0; val < NPE_PHYS_REG; val++) {
> + Â Â Â Â Â Â Â if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0))
> + Â Â Â Â Â Â Â Â Â Â Â return -ETIMEDOUT;
> + Â Â Â Â Â Â Â /* address is either 0 or 4 */
> + Â Â Â Â Â Â Â if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0))
> + Â Â Â Â Â Â Â Â Â Â Â return -ETIMEDOUT;
> + Â Â Â }
> +
> + Â Â Â /* Reset the context store = each context's Context Store registers */
> +
> + Â Â Â /* Context 0 has no STARTPC. Instead, this value is used to set NextPC
> + Â Â Â Â Âfor Background ECS, to set where NPE starts executing code */
> + Â Â Â val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG);
> + Â Â Â val &= ~ECS_REG_0_NEXTPC_MASK;
> + Â Â Â val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK;
> + Â Â Â npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val);
> +
> + Â Â Â for (i = 0; i < 16; i++) {
> + Â Â Â Â Â Â Â if (i) { /* Context 0 has no STEVT nor STARTPC */
> + Â Â Â Â Â Â Â Â Â Â Â /* STEVT = off, 0x80 */
> + Â Â Â Â Â Â Â Â Â Â Â if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i))
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â return -ETIMEDOUT;
> + Â Â Â Â Â Â Â Â Â Â Â if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i))
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â return -ETIMEDOUT;
> + Â Â Â Â Â Â Â }
> + Â Â Â Â Â Â Â /* REGMAP = d0->p0, d8->p2, d16->p4 */
> + Â Â Â Â Â Â Â if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i))
> + Â Â Â Â Â Â Â Â Â Â Â return -ETIMEDOUT;
> + Â Â Â Â Â Â Â if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i))
> + Â Â Â Â Â Â Â Â Â Â Â return -ETIMEDOUT;
> + Â Â Â }
> +
> + Â Â Â /* post exec */
> + Â Â Â /* clear active bit in debug level */
> + Â Â Â npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0);
> + Â Â Â /* clear the pipeline */
> + Â Â Â __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
> + Â Â Â /* restore previous values */
> + Â Â Â __raw_writel(exec_count, &npe->regs->exec_count);
> + Â Â Â npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2);
> +
> + Â Â Â /* write reset values to Execution Context Stack registers */
> + Â Â Â for (val = 0; val < ARRAY_SIZE(ecs_reset); val++)
> + Â Â Â Â Â Â Â npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â ecs_reset[val].val);
> +
> + Â Â Â /* clear the profile counter */
> + Â Â Â __raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd);
> +
> + Â Â Â __raw_writel(0, &npe->regs->exec_count);
> + Â Â Â __raw_writel(0, &npe->regs->action_points[0]);
> + Â Â Â __raw_writel(0, &npe->regs->action_points[1]);
> + Â Â Â __raw_writel(0, &npe->regs->action_points[2]);
> + Â Â Â __raw_writel(0, &npe->regs->action_points[3]);
> + Â Â Â __raw_writel(0, &npe->regs->watch_count);
> +
> + Â Â Â val = ixp4xx_read_feature_bits();
> + Â Â Â /* reset the NPE */
> + Â Â Â ixp4xx_write_feature_bits(val &
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ~(IXP4XX_FEATURE_RESET_NPEA << npe->id));
> + Â Â Â /* deassert reset */
> + Â Â Â ixp4xx_write_feature_bits(val |
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (IXP4XX_FEATURE_RESET_NPEA << npe->id));
> + Â Â Â for (i = 0; i < MAX_RETRIES; i++) {
> + Â Â Â Â Â Â Â if (ixp4xx_read_feature_bits() &
> + Â Â Â Â Â Â Â Â Â (IXP4XX_FEATURE_RESET_NPEA << npe->id))
> + Â Â Â Â Â Â Â Â Â Â Â break; /* NPE is back alive */
> + Â Â Â Â Â Â Â udelay(1);
> + Â Â Â }
> + Â Â Â if (i == MAX_RETRIES)
> + Â Â Â Â Â Â Â return -ETIMEDOUT;
> +
> + Â Â Â npe_stop(npe);
> +
> + Â Â Â /* restore NPE configuration bus Control Register - parity settings */
> + Â Â Â __raw_writel(ctl, &npe->regs->messaging_control);
> + Â Â Â return 0;
> +}
> +
> +
> +int npe_send_message(struct npe *npe, const void *msg, const char *what)
> +{
> + Â Â Â const u32 *send = msg;
> + Â Â Â int cycles = 0;
> +
> + Â Â Â debug_msg(npe, "Trying to send message %s [%08X:%08X]\n",
> + Â Â Â Â Â Â Â Â what, send[0], send[1]);
> +
> + Â Â Â if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) {
> + Â Â Â Â Â Â Â debug_msg(npe, "NPE input FIFO not empty\n");
> + Â Â Â Â Â Â Â return -EIO;
> + Â Â Â }
> +
> + Â Â Â __raw_writel(send[0], &npe->regs->in_out_fifo);
> +
> + Â Â Â if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) {
> + Â Â Â Â Â Â Â debug_msg(npe, "NPE input FIFO full\n");
> + Â Â Â Â Â Â Â return -EIO;
> + Â Â Â }
> +
> + Â Â Â __raw_writel(send[1], &npe->regs->in_out_fifo);
> +
> + Â Â Â while ((cycles < MAX_RETRIES) &&
> + Â Â Â Â Â Â Â(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) {
> + Â Â Â Â Â Â Â udelay(1);
> + Â Â Â Â Â Â Â cycles++;
> + Â Â Â }
> +
> + Â Â Â if (cycles == MAX_RETRIES) {
> + Â Â Â Â Â Â Â debug_msg(npe, "Timeout sending message\n");
> + Â Â Â Â Â Â Â return -ETIMEDOUT;
> + Â Â Â }
> +
> +#if DEBUG_MSG > 1
> + Â Â Â debug_msg(npe, "Sending a message took %i cycles\n", cycles);
> +#endif
> + Â Â Â return 0;
> +}
> +
> +int npe_recv_message(struct npe *npe, void *msg, const char *what)
> +{
> + Â Â Â u32 *recv = msg;
> + Â Â Â int cycles = 0, cnt = 0;
> +
> + Â Â Â debug_msg(npe, "Trying to receive message %s\n", what);
> +
> + Â Â Â while (cycles < MAX_RETRIES) {
> + Â Â Â Â Â Â Â if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) {
> + Â Â Â Â Â Â Â Â Â Â Â recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo);
> + Â Â Â Â Â Â Â Â Â Â Â if (cnt == 2)
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â break;
> + Â Â Â Â Â Â Â } else {
> + Â Â Â Â Â Â Â Â Â Â Â udelay(1);
> + Â Â Â Â Â Â Â Â Â Â Â cycles++;
> + Â Â Â Â Â Â Â }
> + Â Â Â }
> +
> + Â Â Â switch(cnt) {
> + Â Â Â case 1:
> + Â Â Â Â Â Â Â debug_msg(npe, "Received [%08X]\n", recv[0]);
> + Â Â Â Â Â Â Â break;
> + Â Â Â case 2:
> + Â Â Â Â Â Â Â debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]);
> + Â Â Â Â Â Â Â break;
> + Â Â Â }
> +
> + Â Â Â if (cycles == MAX_RETRIES) {
> + Â Â Â Â Â Â Â debug_msg(npe, "Timeout waiting for message\n");
> + Â Â Â Â Â Â Â return -ETIMEDOUT;
> + Â Â Â }
> +
> +#if DEBUG_MSG > 1
> + Â Â Â debug_msg(npe, "Receiving a message took %i cycles\n", cycles);
> +#endif
> + Â Â Â return 0;
> +}
> +
> +int npe_send_recv_message(struct npe *npe, void *msg, const char *what)
> +{
> + Â Â Â int result;
> + Â Â Â u32 *send = msg, recv[2];
> +
> + Â Â Â if ((result = npe_send_message(npe, msg, what)) != 0)
> + Â Â Â Â Â Â Â return result;
> + Â Â Â if ((result = npe_recv_message(npe, recv, what)) != 0)
> + Â Â Â Â Â Â Â return result;
> +
> + Â Â Â if ((recv[0] != send[0]) || (recv[1] != send[1])) {
> + Â Â Â Â Â Â Â debug_msg(npe, "Message %s: unexpected message received\n",
> + Â Â Â Â Â Â Â Â Â Â Â Â what);
> + Â Â Â Â Â Â Â return -EIO;
> + Â Â Â }
> + Â Â Â return 0;
> +}
> +
> +
> +int npe_load_firmware(struct npe *npe)
> +{
> + Â Â Â struct dl_block {
> + Â Â Â Â Â Â Â u32 type;
> + Â Â Â Â Â Â Â u32 offset;
> + Â Â Â } *blk;
> +
> + Â Â Â struct dl_image {
> + Â Â Â Â Â Â Â u32 magic;
> + Â Â Â Â Â Â Â u32 id;
> + Â Â Â Â Â Â Â u32 size;
> + Â Â Â Â Â Â Â union {
> + Â Â Â Â Â Â Â Â Â Â Â u32 data[0];
> + Â Â Â Â Â Â Â Â Â Â Â struct dl_block blocks[0];
> + Â Â Â Â Â Â Â };
> + Â Â Â } *image;
> +
> + Â Â Â struct dl_codeblock {
> + Â Â Â Â Â Â Â u32 npe_addr;
> + Â Â Â Â Â Â Â u32 size;
> + Â Â Â Â Â Â Â u32 data[0];
> + Â Â Â } *cb;
> +
> + Â Â Â int i, j, err, data_size, instr_size, blocks, table_end;
> + Â Â Â u32 cmd;
> + Â Â Â char name[5 /* "/dev/" */ + NPE_NAME_LENGTH + 1 /* NUL */];
> + Â Â Â size_t image_size;
> +
> + Â Â Â sprintf(name, "/dev/%s", npe->name);
> + Â Â Â if (!(image = read_file(name, &image_size))) {
> + Â Â Â Â Â Â Â print_npe(npe, "bad or missing microcode file %s", name);
> + Â Â Â Â Â Â Â return -EIO;
> + Â Â Â }
> +
> + Â Â Â err = -EINVAL;
> + Â Â Â if (image_size < sizeof(struct dl_image)) {
> + Â Â Â Â Â Â Â print_npe(npe, "incomplete microcode file %s\n", name);
> + Â Â Â Â Â Â Â goto err;
> + Â Â Â }
> +
> +#if DEBUG_FW
> + Â Â Â print_npe(npe, "microcode: %08X %08X %08X (0x%X bytes)\n",
> + Â Â Â Â Â Â Â Â image->magic, image->id, image->size, image->size * 4);
> +#endif
> +
> + Â Â Â if (image->magic == swab32(FW_MAGIC)) { /* swapped file */
> + Â Â Â Â Â Â Â image->id = swab32(image->id);
> + Â Â Â Â Â Â Â image->size = swab32(image->size);
> + Â Â Â } else if (image->magic != FW_MAGIC) {
> + Â Â Â Â Â Â Â print_npe(npe, "bad microcode file %s magic: 0x%X\n", name, image->magic);
> + Â Â Â Â Â Â Â goto err;
> + Â Â Â }
> + Â Â Â if ((image->size * 4 + sizeof(struct dl_image)) > image_size) {
> + Â Â Â Â Â Â Â print_npe(npe, "incomplete microcode file %s\n", name);
> + Â Â Â Â Â Â Â goto err;
> + Â Â Â }
> + Â Â Â if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) {
> + Â Â Â Â Â Â Â print_npe(npe, "NPE ID mismatch in microcode file %s\n", name);
> + Â Â Â Â Â Â Â goto err;
> + Â Â Â }
> + Â Â Â if (image->magic == swab32(FW_MAGIC))
> + Â Â Â Â Â Â Â for (i = 0; i < image->size; i++)
> + Â Â Â Â Â Â Â Â Â Â Â image->data[i] = swab32(image->data[i]);
> +
> + Â Â Â if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF /* device ID */)) {
> + Â Â Â Â Â Â Â print_npe(npe, "IXP43x/IXP46x microcode ignored on IXP42x\n");
> + Â Â Â Â Â Â Â goto err;
> + Â Â Â }
> +
> + Â Â Â if (npe_running(npe)) {
> + Â Â Â Â Â Â Â print_npe(npe, "unable to load microcode file %s, NPE is already running\n", name);
> + Â Â Â Â Â Â Â err = -EBUSY;
> + Â Â Â Â Â Â Â goto err;
> + Â Â Â }
> +
> + Â Â Â if (cpu_is_ixp42x()) {
> + Â Â Â Â Â Â Â if (!npe->id)
> + Â Â Â Â Â Â Â Â Â Â Â instr_size = NPE_A_42X_INSTR_SIZE;
> + Â Â Â Â Â Â Â else
> + Â Â Â Â Â Â Â Â Â Â Â instr_size = NPE_B_AND_C_42X_INSTR_SIZE;
> + Â Â Â Â Â Â Â data_size = NPE_42X_DATA_SIZE;
> + Â Â Â } else {
> + Â Â Â Â Â Â Â instr_size = NPE_46X_INSTR_SIZE;
> + Â Â Â Â Â Â Â data_size = NPE_46X_DATA_SIZE;
> + Â Â Â }
> +
> + Â Â Â for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size;
> + Â Â Â Â Â Âblocks++)
> + Â Â Â Â Â Â Â if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF)
> + Â Â Â Â Â Â Â Â Â Â Â break;
> + Â Â Â if (blocks * sizeof(struct dl_block) / 4 >= image->size) {
> + Â Â Â Â Â Â Â print_npe(npe, "microcode EOF block marker not found\n");
> + Â Â Â Â Â Â Â goto err;
> + Â Â Â }
> +
> +#if DEBUG_FW
> + Â Â Â print_npe(npe, "%i microcode blocks found\n", blocks);
> +#endif
> +
> + Â Â Â table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */;
> + Â Â Â for (i = 0, blk = image->blocks; i < blocks; i++, blk++) {
> + Â Â Â Â Â Â Â if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4
> + Â Â Â Â Â Â Â Â Â || blk->offset < table_end) {
> + Â Â Â Â Â Â Â Â Â Â Â print_npe(npe, "invalid offset 0x%X of "
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "microcode block #%i\n", blk->offset, i);
> + Â Â Â Â Â Â Â Â Â Â Â goto err;
> + Â Â Â Â Â Â Â }
> +
> + Â Â Â Â Â Â Â cb = (struct dl_codeblock*)&image->data[blk->offset];
> + Â Â Â Â Â Â Â if (blk->type == FW_BLOCK_TYPE_INSTR) {
> + Â Â Â Â Â Â Â Â Â Â Â if (cb->npe_addr + cb->size > instr_size)
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â goto too_big;
> + Â Â Â Â Â Â Â Â Â Â Â cmd = CMD_WR_INS_MEM;
> + Â Â Â Â Â Â Â } else if (blk->type == FW_BLOCK_TYPE_DATA) {
> + Â Â Â Â Â Â Â Â Â Â Â if (cb->npe_addr + cb->size > data_size)
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â goto too_big;
> + Â Â Â Â Â Â Â Â Â Â Â cmd = CMD_WR_DATA_MEM;
> + Â Â Â Â Â Â Â } else {
> + Â Â Â Â Â Â Â Â Â Â Â print_npe(npe, "invalid microcode block #%i type 0x%X\n",
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â i, blk->type);
> + Â Â Â Â Â Â Â Â Â Â Â goto err;
> + Â Â Â Â Â Â Â }
> + Â Â Â Â Â Â Â if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) {
> + Â Â Â Â Â Â Â Â Â Â Â print_npe(npe, "microcode block #%i doesn't "
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "fit in microcode image: type %c, start 0x%X,"
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â " length 0x%X\n", i,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â cb->npe_addr, cb->size);
> + Â Â Â Â Â Â Â Â Â Â Â goto err;
> + Â Â Â Â Â Â Â }
> +
> + Â Â Â Â Â Â Â for (j = 0; j < cb->size; j++)
> + Â Â Â Â Â Â Â Â Â Â Â npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]);
> + Â Â Â }
> +
> + Â Â Â npe_start(npe);
> + Â Â Â if (!npe_running(npe))
> + Â Â Â Â Â Â Â print_npe(npe, "unable to start\n");
> + Â Â Â free(image);
> + Â Â Â return 0;
> +
> +too_big:
> + Â Â Â print_npe(npe, "microcode block #%i doesn't fit in NPE "
> + Â Â Â Â Â Â Â Â "memory: type %c, start 0x%X, length 0x%X\n", i,
> + Â Â Â Â Â Â Â Â blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
> + Â Â Â Â Â Â Â Â cb->npe_addr, cb->size);
> +err:
> + Â Â Â free(image);
> + Â Â Â return err;
> +}
> +
> +
> +struct npe *npe_request(int id)
> +{
> + Â Â Â if (id < NPE_COUNT)
> + Â Â Â Â Â Â Â if (npe_tab[id].valid)
> + Â Â Â Â Â Â Â Â Â Â Â return &npe_tab[id];
> + Â Â Â return NULL;
> +}
> +
> +static int __init npe_init(void)
> +{
> + Â Â Â int i;
> +
> + Â Â Â for (i = 0; i < NPE_COUNT; i++) {
> + Â Â Â Â Â Â Â struct npe *npe = &npe_tab[i];
> + Â Â Â Â Â Â Â if (!(ixp4xx_read_feature_bits() & (IXP4XX_FEATURE_RESET_NPEA << i)))
> + Â Â Â Â Â Â Â Â Â Â Â continue; /* NPE already disabled or not present */
> + Â Â Â Â Â Â Â if (npe_reset(npe))
> + Â Â Â Â Â Â Â Â Â Â Â continue;
> + Â Â Â Â Â Â Â npe->valid = 1;
> + Â Â Â }
> + Â Â Â return 0;
> +}
> +
> +coredevice_initcall(npe_init);
> diff --git a/arch/arm/mach-ixp4xx/qmgr.c b/arch/arm/mach-ixp4xx/qmgr.c
> new file mode 100644
> index 0000000..49cba60
> --- /dev/null
> +++ b/arch/arm/mach-ixp4xx/qmgr.c
> @@ -0,0 +1,269 @@
> +/*
> + * Intel IXP4xx Queue Manager driver for Linux
> + *
> + * Copyright (C) 2007 Krzysztof Halasa <khc@xxxxxxxxx>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of version 2 of the GNU General Public License
> + * as published by the Free Software Foundation.
> + */
> +
> +#include <init.h>
> +#include <errno.h>
> +#include <mach/qmgr.h>
> +
> +static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
> +
> +#if DEBUG_QMGR
> +char qmgr_queue_descs[HALF_QUEUES][32];
> +#endif
> +
> +#ifdef CONFIG_USE_IRQ
> +
> +static void (*irq_handlers[HALF_QUEUES])(void *pdev);
> +static void *irq_pdevs[HALF_QUEUES];
> +
> +#undef fls
> +static inline int fls(int x)
> +{
> + Â Â Â int ret;
> + Â Â Â asm("clz\t%0, %1" : "=r" (ret) : "r" (x) : "cc");
> + Â Â Â ret = 32 - ret;
> + Â Â Â return ret;
> +}
> +
> +
> +void qmgr_set_irq(unsigned int queue, int src,
> + Â Â Â Â Â Â Â Â void (*handler)(void *pdev), void *pdev)
> +{
> + Â Â Â const u32 *reg;
> + Â Â Â int bit;
> + Â Â Â BUG_ON(src > QUEUE_IRQ_SRC_NOT_FULL);
> + Â Â Â reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */
> + Â Â Â bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */
> + Â Â Â __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), reg);
> +
> + Â Â Â irq_handlers[queue] = handler;
> + Â Â Â irq_pdevs[queue] = pdev;
> +}
> +
> +
> +static void qmgr_irq1_a0(void *data)
> +{
> + Â Â Â int i;
> + Â Â Â u32 en_bitmap, src, stat;
> +
> + Â Â Â /* ACK - it may clear any bits so don't rely on it */
> + Â Â Â __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[0]);
> +
> + Â Â Â en_bitmap = qmgr_regs->irqen[0];
> + Â Â Â while (en_bitmap) {
> + Â Â Â Â Â Â Â i = fls(en_bitmap) - 1; /* number of the last "low" queue */
> + Â Â Â Â Â Â Â en_bitmap &= ~BIT(i);
> + Â Â Â Â Â Â Â src = qmgr_regs->irqsrc[i >> 3];
> + Â Â Â Â Â Â Â stat = qmgr_regs->stat1[i >> 3];
> + Â Â Â Â Â Â Â if (src & 4) /* the IRQ condition is inverted */
> + Â Â Â Â Â Â Â Â Â Â Â stat = ~stat;
> + Â Â Â Â Â Â Â if (stat & BIT(src & 3))
> + Â Â Â Â Â Â Â Â Â Â Â irq_handlers[i](irq_pdevs[i]);
> + Â Â Â }
> +}
> +
> +
> +static void qmgr_irq1(void *data)
> +{
> + Â Â Â int i;
> + Â Â Â u32 req_bitmap = __raw_readl(&qmgr_regs->irqstat[0]);
> +
> + Â Â Â if (!req_bitmap)
> + Â Â Â Â Â Â Â return;
> + Â Â Â __raw_writel(req_bitmap, &qmgr_regs->irqstat[0]); /* ACK */
> +
> + Â Â Â while (req_bitmap) {
> + Â Â Â Â Â Â Â i = fls(req_bitmap) - 1; /* number of the last queue */
> + Â Â Â Â Â Â Â req_bitmap &= ~BIT(i);
> + Â Â Â Â Â Â Â irq_handlers[i](irq_pdevs[i]);
> + Â Â Â }
> +}
> +
> +
> +void qmgr_enable_irq(unsigned int queue)
> +{
> + Â Â Â u32 mask = 1 << queue;
> +
> + Â Â Â __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) | mask,
> + Â Â Â Â Â Â Â Â Â Â&qmgr_regs->irqen[0]);
> +}
> +
> +void qmgr_disable_irq(unsigned int queue)
> +{
> + Â Â Â u32 mask = 1 << queue;
> +
> + Â Â Â __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~mask,
> + Â Â Â Â Â Â Â Â Â Â&qmgr_regs->irqen[0]);
> + Â Â Â __raw_writel(mask, &qmgr_regs->irqstat[0]); /* clear */
> +}
> +
> +#endif /* CONFIG_USE_IRQ */
> +
> +static inline void shift_mask(u32 *mask)
> +{
> + Â Â Â mask[3] = mask[3] << 1 | mask[2] >> 31;
> + Â Â Â mask[2] = mask[2] << 1 | mask[1] >> 31;
> + Â Â Â mask[1] = mask[1] << 1 | mask[0] >> 31;
> + Â Â Â mask[0] <<= 1;
> +}
> +
> +#if DEBUG_QMGR
> +void qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
> + Â Â Â Â Â Â Â Â Â Â Â unsigned int nearly_empty_watermark,
> + Â Â Â Â Â Â Â Â Â Â Â unsigned int nearly_full_watermark,
> + Â Â Â Â Â Â Â Â Â Â Â const char *desc_format, const char* name)
> +#else
> +void __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
> + Â Â Â Â Â Â Â Â Â Â Â Â unsigned int nearly_empty_watermark,
> + Â Â Â Â Â Â Â Â Â Â Â Â unsigned int nearly_full_watermark)
> +#endif
> +{
> + Â Â Â u32 cfg, addr = 0, mask[4]; /* in 16-dwords */
> +
> + Â Â Â BUG_ON(queue >= HALF_QUEUES);
> + Â Â Â BUG_ON((nearly_empty_watermark | nearly_full_watermark) & ~7);
> +
> + Â Â Â switch (len) {
> + Â Â Â case Â16:
> + Â Â Â Â Â Â Â cfg = 0 << 24;
> + Â Â Â Â Â Â Â mask[0] = 0x1;
> + Â Â Â Â Â Â Â break;
> + Â Â Â case Â32:
> + Â Â Â Â Â Â Â cfg = 1 << 24;
> + Â Â Â Â Â Â Â mask[0] = 0x3;
> + Â Â Â Â Â Â Â break;
> + Â Â Â case Â64:
> + Â Â Â Â Â Â Â cfg = 2 << 24;
> + Â Â Â Â Â Â Â mask[0] = 0xF;
> + Â Â Â Â Â Â Â break;
> + Â Â Â case 128:
> + Â Â Â Â Â Â Â cfg = 3 << 24;
> + Â Â Â Â Â Â Â mask[0] = 0xFF;
> + Â Â Â Â Â Â Â break;
> + Â Â Â default:
> + Â Â Â Â Â Â Â BUG();
> + Â Â Â }
> +
> + Â Â Â cfg |= nearly_empty_watermark << 26;
> + Â Â Â cfg |= nearly_full_watermark << 29;
> + Â Â Â len /= 16; /* in 16-dwords: 1, 2, 4 or 8 */
> + Â Â Â mask[1] = mask[2] = mask[3] = 0;
> +
> + Â Â Â BUG_ON(__raw_readl(&qmgr_regs->sram[queue]));
> +
> + Â Â Â while (1) {
> + Â Â Â Â Â Â Â if (!(used_sram_bitmap[0] & mask[0]) &&
> + Â Â Â Â Â Â Â Â Â !(used_sram_bitmap[1] & mask[1]) &&
> + Â Â Â Â Â Â Â Â Â !(used_sram_bitmap[2] & mask[2]) &&
> + Â Â Â Â Â Â Â Â Â !(used_sram_bitmap[3] & mask[3]))
> + Â Â Â Â Â Â Â Â Â Â Â break; /* found free space */
> +
> + Â Â Â Â Â Â Â addr++;
> + Â Â Â Â Â Â Â shift_mask(mask);
> + Â Â Â Â Â Â Â if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) {
> + Â Â Â Â Â Â Â Â Â Â Â fprintf(stderr, "qmgr: no free SRAM space for"
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â " queue %i\n", queue);
> + Â Â Â Â Â Â Â Â Â Â Â BUG();
> + Â Â Â Â Â Â Â }
> + Â Â Â }
> +
> + Â Â Â used_sram_bitmap[0] |= mask[0];
> + Â Â Â used_sram_bitmap[1] |= mask[1];
> + Â Â Â used_sram_bitmap[2] |= mask[2];
> + Â Â Â used_sram_bitmap[3] |= mask[3];
> + Â Â Â __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);
> +#if DEBUG_QMGR
> + Â Â Â /* no snprintf() */
> + Â Â Â sprintf(qmgr_queue_descs[queue], desc_format, name);
> + Â Â Â fprintf(stderr, "qmgr: requested queue %s(%i) addr = 0x%02X\n",
> + Â Â Â Â Â Â Â qmgr_queue_descs[queue], queue, addr);
> +#endif
> +}
> +
> +void qmgr_release_queue(unsigned int queue)
> +{
> + Â Â Â u32 cfg, addr, mask[4];
> +
> + Â Â Â BUG_ON(queue >= HALF_QUEUES); /* not in valid range */
> +
> + Â Â Â cfg = __raw_readl(&qmgr_regs->sram[queue]);
> + Â Â Â addr = (cfg >> 14) & 0xFF;
> +
> + Â Â Â BUG_ON(!addr); /* not requested */
> +
> + Â Â Â switch ((cfg >> 24) & 3) {
> + Â Â Â case 0: mask[0] = 0x1; break;
> + Â Â Â case 1: mask[0] = 0x3; break;
> + Â Â Â case 2: mask[0] = 0xF; break;
> + Â Â Â case 3: mask[0] = 0xFF; break;
> + Â Â Â }
> +
> + Â Â Â mask[1] = mask[2] = mask[3] = 0;
> +
> + Â Â Â while (addr--)
> + Â Â Â Â Â Â Â shift_mask(mask);
> +
> +#if DEBUG_QMGR
> + Â Â Â fprintf(stderr, "qmgr: releasing queue %s(%i)\n",
> + Â Â Â Â Â Â Â qmgr_queue_descs[queue], queue);
> + Â Â Â qmgr_queue_descs[queue][0] = '\x0';
> +#endif
> + Â Â Â __raw_writel(0, &qmgr_regs->sram[queue]);
> +
> + Â Â Â used_sram_bitmap[0] &= ~mask[0];
> + Â Â Â used_sram_bitmap[1] &= ~mask[1];
> + Â Â Â used_sram_bitmap[2] &= ~mask[2];
> + Â Â Â used_sram_bitmap[3] &= ~mask[3];
> +#ifdef CONFIG_USE_IRQ
> + Â Â Â irq_handlers[queue] = NULL; /* catch IRQ bugs */
> +#endif
> +
> + Â Â Â while ((addr = qmgr_get_entry(queue)))
> + Â Â Â Â Â Â Â fprintf(stderr, "qmgr: released queue %i not empty: 0x%08X\n",
> + Â Â Â Â Â Â Â Â Â Â Â queue, addr);
> +}
> +
> +static int __init qmgr_init(void)
> +{
> + Â Â Â int i;
> +#ifdef CONFIG_USE_IRQ
> + Â Â Â interrupt_handler_t *handler;
> +#endif
> +
> + Â Â Â /* reset qmgr registers */
> + Â Â Â for (i = 0; i < 4; i++) {
> + Â Â Â Â Â Â Â __raw_writel(0x33333333, &qmgr_regs->stat1[i]);
> + Â Â Â Â Â Â Â __raw_writel(0, &qmgr_regs->irqsrc[i]);
> + Â Â Â }
> + Â Â Â for (i = 0; i < 2; i++) {
> + Â Â Â Â Â Â Â __raw_writel(0, &qmgr_regs->stat2[i]);
> + Â Â Â Â Â Â Â __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */
> + Â Â Â Â Â Â Â __raw_writel(0, &qmgr_regs->irqen[i]);
> + Â Â Â }
> +
> + Â Â Â __raw_writel(0xFFFFFFFF, &qmgr_regs->statne_h);
> + Â Â Â __raw_writel(0, &qmgr_regs->statf_h);
> +
> + Â Â Â for (i = 0; i < QUEUES; i++)
> + Â Â Â Â Â Â Â __raw_writel(0, &qmgr_regs->sram[i]);
> +
> +#ifdef CONFIG_USE_IRQ
> + Â Â Â if (cpu_is_ixp42x_rev_a0())
> + Â Â Â Â Â Â Â handler = qmgr_irq1_a0;
> + Â Â Â else
> + Â Â Â Â Â Â Â handler = qmgr_irq1;
> +
> + Â Â Â irq_install_handler(IXP425_QM1_IRQ, handler, NULL);
> +#endif
> + Â Â Â used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */
> + Â Â Â return 0;
> +}
> +
> +coredevice_initcall(qmgr_init);
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index 69f3352..df6e42c 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -77,6 +77,14 @@ config DRIVER_NET_MACB
> Â Â Â Âdepends on HAS_MACB
> Â Â Â Âselect MIIDEV
>
> +config DRIVER_NET_IXP4XX_ETH
> + Â Â Â tristate "Intel IXP4xx Ethernet support"
> + Â Â Â depends on ARCH_IXP4XX && IXP4XX_NPE && IXP4XX_QMGR
> + Â Â Â select MIIDEV
> + Â Â Â help
> + Â Â Â Â Say Y here if you want to use built-in Ethernet ports
> + Â Â Â Â on IXP4xx processor.
> +
> Âconfig DRIVER_NET_TAP
> Â Â Â Âbool "tap Ethernet driver"
> Â Â Â Âdepends on LINUX
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index 96d3d32..97cb44b 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -11,3 +11,4 @@ obj-$(CONFIG_DRIVER_NET_MACB) Â Â Â Â += macb.o
> Âobj-$(CONFIG_DRIVER_NET_TAP) Â Â Â Â Â += tap.o
> Âobj-$(CONFIG_MIIDEV) Â Â Â Â Â Â Â Â Â += miidev.o
> Âobj-$(CONFIG_NET_USB) Â Â Â Â Â Â Â Â Â+= usb/
> +obj-$(CONFIG_DRIVER_NET_IXP4XX_ETH) Â Â+= ixp4xx_eth.o
> diff --git a/drivers/net/ixp4xx_eth.c b/drivers/net/ixp4xx_eth.c
> new file mode 100644
> index 0000000..71e6d92
> --- /dev/null
> +++ b/drivers/net/ixp4xx_eth.c
> @@ -0,0 +1,763 @@
> +/*
> + * Intel IXP4xx Ethernet driver for Linux
> + *
> + * Copyright (C) 2007 Krzysztof Halasa <khc@xxxxxxxxx>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of version 2 of the GNU General Public License
> + * as published by the Free Software Foundation.
> + *
> + * Ethernet port config (0x00 is not present on IXP42X):
> + *
> + * logical port        Â0x00      Â0x10      Â0x20
> + * NPE Â Â Â Â Â Â Â Â 0 (NPE-A) Â Â Â 1 (NPE-B) Â Â Â 2 (NPE-C)
> + * physical port    2        0        1
> + * RX queue (variable) 20 Â Â Â Â Â Â Â21 Â Â Â Â Â Â Â22
> + * TX queue      Â23       Â24       Â25
> + * RX-free queue    26       Â27       Â28
> + * TX-done queue is always 31, per-port RX queue is configurable
> + *
> + *
> + * Queue entries:
> + * bits 0 -> 1 Â- NPE ID (RX and TX-done)
> + * bits 0 -> 2 Â- priority (TX, per 802.1D)
> + * bits 3 -> 4 Â- port ID (user-set?)
> + * bits 5 -> 31 - physical descriptor address
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +#include <malloc.h>
> +#include <miidev.h>
> +#include <net.h>
> +#include <errno.h>
> +#include <mach/ixp4xx-regs.h>
> +#include <mach/platform.h>
> +#include <mach/cpu.h>
> +#include <mach/npe.h>
> +#include <mach/qmgr.h>
> +
> +#define DEBUG_DESC Â Â Â Â Â Â 0
> +#define DEBUG_RX Â Â Â Â Â Â Â 0
> +#define DEBUG_TX Â Â Â Â Â Â Â 0
> +#define DEBUG_PKT_BYTES Â Â Â Â Â Â Â Â0
> +#define DEBUG_MDIO Â Â Â Â Â Â 0
> +#define DEBUG_OPEN Â Â Â Â Â Â 0
> +#define DEBUG_CLOSE Â Â Â Â Â Â0
> +
> +#define RX_DESCS Â Â Â Â Â Â Â 16 /* also length of all RX queues */
> +#define TX_DESCS Â Â Â Â Â Â Â 16 /* also length of all TX queues */
> +#define TXDONE_QUEUE_LEN Â Â Â 16 /* dwords */
> +
> +#define MAX_MRU Â Â Â Â Â Â Â Â Â Â Â Â1536 /* 0x600 */
> +#define RX_BUFF_SIZE Â Â Â Â Â MAX_MRU
> +
> +#define MAX_MDIO_RETRIES Â Â Â 100 /* microseconds, typically 30 cycles */
> +#define MAX_CLOSE_WAIT Â Â Â Â 1000 /* microseconds, typically 2-3 cycles */
> +#define ETH_ALEN Â Â Â Â Â Â Â 6
> +
> +#define PHYSICAL_ID(port) Â Â Â(((port)->npe->id + 2) % 3)
> +#define LOGICAL_ID(port) Â Â Â ((port)->npe->id << 4)
> +#define RX_QUEUE(port) Â Â Â Â ((port)->npe->id + 20) /* can be changed */
> +#define TX_QUEUE(port) Â Â Â Â ((port)->npe->id + 23)
> +#define RXFREE_QUEUE(port) Â Â ((port)->npe->id + 26)
> +#define TXDONE_QUEUE Â Â Â Â Â 31
> +
> +/* TX Control Registers */
> +#define TX_CNTRL0_TX_EN Â Â Â Â Â Â Â Â0x01
> +#define TX_CNTRL0_HALFDUPLEX Â 0x02
> +#define TX_CNTRL0_RETRY Â Â Â Â Â Â Â Â0x04
> +#define TX_CNTRL0_PAD_EN Â Â Â 0x08
> +#define TX_CNTRL0_APPEND_FCS Â 0x10
> +#define TX_CNTRL0_2DEFER Â Â Â 0x20
> +#define TX_CNTRL0_RMII Â Â Â Â 0x40 /* reduced MII */
> +#define TX_CNTRL1_RETRIES Â Â Â0x0F /* 4 bits */
> +
> +/* RX Control Registers */
> +#define RX_CNTRL0_RX_EN Â Â Â Â Â Â Â Â0x01
> +#define RX_CNTRL0_PADSTRIP_EN Â0x02
> +#define RX_CNTRL0_SEND_FCS Â Â 0x04
> +#define RX_CNTRL0_PAUSE_EN Â Â 0x08
> +#define RX_CNTRL0_LOOP_EN Â Â Â0x10
> +#define RX_CNTRL0_ADDR_FLTR_EN 0x20
> +#define RX_CNTRL0_RX_RUNT_EN Â 0x40
> +#define RX_CNTRL0_BCAST_DIS Â Â0x80
> +#define RX_CNTRL1_DEFER_EN Â Â 0x01
> +
> +/* Core Control Register */
> +#define CORE_RESET Â Â Â Â Â Â 0x01
> +#define CORE_RX_FIFO_FLUSH Â Â 0x02
> +#define CORE_TX_FIFO_FLUSH Â Â 0x04
> +#define CORE_SEND_JAM Â Â Â Â Â0x08
> +#define CORE_MDC_EN Â Â Â Â Â Â0x10 /* MDIO using NPE-B ETH-0 only */
> +
> +#define DEFAULT_TX_CNTRL0 Â Â Â(TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | Â Â Â \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂTX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂTX_CNTRL0_2DEFER)
> +#define DEFAULT_RX_CNTRL0 Â Â ÂRX_CNTRL0_RX_EN
> +#define DEFAULT_CORE_CNTRL Â Â CORE_MDC_EN
> +
> +
> +/* NPE message codes */
> +#define NPE_GETSTATUS Â Â Â Â Â Â Â Â Â 0x00
> +#define NPE_EDB_SETPORTADDRESS Â Â Â Â Â0x01
> +#define NPE_EDB_GETMACADDRESSDATABASE Â 0x02
> +#define NPE_EDB_SETMACADDRESSSDATABASE Â0x03
> +#define NPE_GETSTATS Â Â Â Â Â Â Â Â Â Â0x04
> +#define NPE_RESETSTATS Â Â Â Â Â Â Â Â Â0x05
> +#define NPE_SETMAXFRAMELENGTHS Â Â Â Â Â0x06
> +#define NPE_VLAN_SETRXTAGMODE Â Â Â Â Â 0x07
> +#define NPE_VLAN_SETDEFAULTRXVID Â Â Â Â0x08
> +#define NPE_VLAN_SETPORTVLANTABLEENTRY Â0x09
> +#define NPE_VLAN_SETPORTVLANTABLERANGE Â0x0A
> +#define NPE_VLAN_SETRXQOSENTRY Â Â Â Â Â0x0B
> +#define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
> +#define NPE_STP_SETBLOCKINGSTATE Â Â Â Â0x0D
> +#define NPE_FW_SETFIREWALLMODE Â Â Â Â Â0x0E
> +#define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
> +#define NPE_PC_SETAPMACTABLE Â Â Â Â Â Â0x11
> +#define NPE_SETLOOPBACK_MODE Â Â Â Â Â Â0x12
> +#define NPE_PC_SETBSSIDTABLE Â Â Â Â Â Â0x13
> +#define NPE_ADDRESS_FILTER_CONFIG Â Â Â 0x14
> +#define NPE_APPENDFCSCONFIG Â Â Â Â Â Â 0x15
> +#define NPE_NOTIFY_MAC_RECOVERY_DONE Â Â0x16
> +#define NPE_MAC_RECOVERY_START Â Â Â Â Â0x17
> +
> +struct eth_regs {
> + Â Â Â u32 tx_control[2], __res1[2]; Â Â Â Â Â Â/* 000 */
> + Â Â Â u32 rx_control[2], __res2[2]; Â Â Â Â Â Â/* 010 */
> + Â Â Â u32 random_seed, __res3[3]; Â Â Â Â Â Â Â/* 020 */
> + Â Â Â u32 partial_empty_threshold, __res4; Â Â /* 030 */
> + Â Â Â u32 partial_full_threshold, __res5; Â Â Â/* 038 */
> + Â Â Â u32 tx_start_bytes, __res6[3]; Â Â Â Â Â /* 040 */
> + Â Â Â u32 tx_deferral, rx_deferral, __res7[2]; /* 050 */
> + Â Â Â u32 tx_2part_deferral[2], __res8[2]; Â Â /* 060 */
> + Â Â Â u32 slot_time, __res9[3]; Â Â Â Â Â Â Â Â/* 070 */
> + Â Â Â u32 mdio_command[4]; Â Â Â Â Â Â Â Â Â Â /* 080 */
> + Â Â Â u32 mdio_status[4]; Â Â Â Â Â Â Â Â Â Â Â/* 090 */
> + Â Â Â u32 mcast_mask[6], __res10[2]; Â Â Â Â Â /* 0A0 */
> + Â Â Â u32 mcast_addr[6], __res11[2]; Â Â Â Â Â /* 0C0 */
> + Â Â Â u32 int_clock_threshold, __res12[3]; Â Â /* 0E0 */
> + Â Â Â u32 hw_addr[6], __res13[61]; Â Â Â Â Â Â /* 0F0 */
> + Â Â Â u32 core_control; Â Â Â Â Â Â Â Â Â Â Â Â/* 1FC */
> +};
> +
> +/* NPE message structure */
> +struct msg {
> + Â Â Â u8 cmd, eth_id, params[6];
> +};
> +
> +/* Ethernet packet descriptor, 32 bytes */
> +struct desc {
> + Â Â Â u8 *next; Â Â/* pointer to next buffer, unused */
> +
> + Â Â Â u16 buf_len; /* buffer length */
> + Â Â Â u16 pkt_len; /* packet length */
> + Â Â Â u8 *data; Â Â/* pointer to data buffer in RAM */
> + Â Â Â u8 dest_id;
> + Â Â Â u8 src_id;
> + Â Â Â u16 flags;
> + Â Â Â u8 qos;
> + Â Â Â u8 padlen;
> + Â Â Â u16 vlan_tci;
> +
> + Â Â Â u8 dst_mac[ETH_ALEN], src_mac[ETH_ALEN];
> +};
> +
> +struct port {
> + Â Â Â struct desc rx_desc_tab[RX_DESCS]; /* alignment: 0x10 */
> + Â Â Â struct desc tx_desc_tab[TX_DESCS];
> + Â Â Â u8 *buff_tab;
> + Â Â Â struct eth_regs *regs;
> + Â Â Â struct npe *npe;
> + Â Â Â u8 firmware[4];
> + Â Â Â struct eth_plat_info *pinfo;
> + Â Â Â struct mii_device miidev;
> + Â Â Â struct eth_device eth;
> +};
> +
> +#define rx_buff(port, n) ((port)->buff_tab + MAX_MRU * (n))
> +#define tx_buff(port, n) ((port)->buff_tab + MAX_MRU * (RX_DESCS + (n)))
> +
> +static struct eth_regs *mdio_regs; /* mdio command and status only */
> +
> +static int ixp4xx_mdio_cmd(int write, const struct device_d *dev, unsigned char phy_id,
> + Â Â Â Â Â Â Â Â Â Â Â Â Âunsigned char location, unsigned short value)
> +{
> + Â Â Â int cycles = 0;
> +
> + Â Â Â if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
> + Â Â Â Â Â Â Â fprintf(stderr, "%s%d: MII not ready to transmit\n", dev->name, dev->id);
> + Â Â Â Â Â Â Â return -1;
> + Â Â Â }
> +
> + Â Â Â if (write) {
> + Â Â Â Â Â Â Â __raw_writel(value & 0xFF, &mdio_regs->mdio_command[0]);
> + Â Â Â Â Â Â Â __raw_writel(value >> 8, &mdio_regs->mdio_command[1]);
> + Â Â Â }
> + Â Â Â __raw_writel(((phy_id << 5) | location) & 0xFF,
> + Â Â Â Â Â Â Â Â Â Â&mdio_regs->mdio_command[2]);
> + Â Â Â __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
> + Â Â Â Â Â Â Â Â Â Â&mdio_regs->mdio_command[3]);
> +
> + Â Â Â while ((cycles < MAX_MDIO_RETRIES) &&
> + Â Â Â Â Â Â Â(__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
> + Â Â Â Â Â Â Â udelay(1);
> + Â Â Â Â Â Â Â cycles++;
> + Â Â Â }
> +
> + Â Â Â if (cycles == MAX_MDIO_RETRIES) {
> + Â Â Â Â Â Â Â fprintf(stderr, "%s%d: MII write failed\n", dev->name, dev->id);
> + Â Â Â Â Â Â Â return -1;
> + Â Â Â }
> +
> +#if DEBUG_MDIO
> + Â Â Â fprintf(stderr, "%s%d: mdio_%s() took %i cycles\n", dev->name, dev->id,
> + Â Â Â Â Â Â Â write ? "write" : "read", cycles);
> +#endif
> +
> + Â Â Â if (write)
> + Â Â Â Â Â Â Â return 0;
> +
> + Â Â Â if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
> +#if DEBUG_MDIO
> + Â Â Â Â Â Â Â fprintf(stderr, "%s%d: MII read failed\n", dev->name, dev->id);
> +#endif
> + Â Â Â Â Â Â Â return -1;
> + Â Â Â }
> +
> + Â Â Â value = (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
> + Â Â Â Â Â Â Â ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8);
> +#if DEBUG_MDIO
> + Â Â Â fprintf(stderr, "%s%d: MII read [%i] -> 0x%X\n", dev->name, dev->id, location, value);
> +#endif
> +
> + Â Â Â return value;
> +}
> +
> +static int ixp4xx_mdio_read(struct mii_device *mii, int phy_id, int location)
> +{
> + Â Â Â int ret = ixp4xx_mdio_cmd(0, &mii->dev, phy_id, location, 0);
> + Â Â Â return ret;
> +}
> +
> +static int ixp4xx_mdio_write(struct mii_device *mii, int phy_id, int location, int value)
> +{
> + Â Â Â int ret = ixp4xx_mdio_cmd(1, &mii->dev, phy_id, location, value);
> +#if DEBUG_MDIO
> + Â Â Â fprintf(stderr, "%s%d: MII write [%i] <- 0x%X, err = %i\n",
> + Â Â Â Â Â Â Â mii->dev.name, mii->dev.id, location, value, ret);
> +#endif
> + Â Â Â return ret;
> +}
> +
> +static int ixp4xx_adjust_link(struct eth_device *dev)
> +{
> + Â Â Â struct port *port = dev->priv;
> + Â Â Â int reg, speed, duplex;
> +
> + Â Â Â miidev_wait_aneg(&port->miidev);
> +
> + Â Â Â reg = mii_read(&port->miidev, port->miidev.address, MII_BMSR);
> + Â Â Â if (reg < 0)
> + Â Â Â Â Â Â Â goto err_out;
> + Â Â Â if (!(reg & BMSR_LSTATUS)) {
> + Â Â Â Â Â Â Â printf("%s%d: Link is down", dev->dev.name, dev->dev.id);
> + Â Â Â Â Â Â Â return -1;
> + Â Â Â }
> +
> + Â Â Â reg = mii_read(&port->miidev, port->miidev.address, MII_BMCR);
> + Â Â Â if (reg < 0)
> + Â Â Â Â Â Â Â goto err_out;
> +
> + Â Â Â if (reg & BMCR_ANENABLE) {
> + Â Â Â Â Â Â Â reg = mii_read(&port->miidev, port->miidev.address, MII_LPA);
> + Â Â Â Â Â Â Â if (reg < 0)
> + Â Â Â Â Â Â Â Â Â Â Â goto err_out;
> + Â Â Â Â Â Â Â duplex = reg & LPA_DUPLEX;
> + Â Â Â Â Â Â Â speed = reg & LPA_100 ? 100 : 10;
> + Â Â Â } else {
> + Â Â Â Â Â Â Â duplex = reg & BMCR_FULLDPLX;
> + Â Â Â Â Â Â Â speed = reg & BMCR_SPEED100 ? 100 : 10;
> + Â Â Â }
> +
> + Â Â Â if (duplex)
> + Â Â Â Â Â Â Â __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â&port->regs->tx_control[0]);
> + Â Â Â else
> + Â Â Â Â Â Â Â __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â&port->regs->tx_control[0]);
> +
> + Â Â Â fprintf(stderr, "%s%d: link up, speed %u Mb/s, %s duplex\n",
> + Â Â Â Â Â Â Â dev->dev.name, dev->dev.id, speed, duplex ? "full" : "half");
> + Â Â Â return 0;
> +
> +err_out:
> + Â Â Â printf("%s%d: failed to read MII data\n", dev->dev.name, dev->dev.id);
> + Â Â Â return -EIO;
> +}
> +
> +static inline void debug_pkt(struct eth_device *dev, const char *func,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Âu8 *data, int len)
> +{
> +#if DEBUG_PKT_BYTES
> + Â Â Â int i;
> +
> + Â Â Â fprintf(stderr, "%s%d: %s(%4i) ", dev->dev.name, dev->dev.id, func, len);
> + Â Â Â for (i = 0; i < len; i++) {
> + Â Â Â Â Â Â Â if (i >= DEBUG_PKT_BYTES)
> + Â Â Â Â Â Â Â Â Â Â Â break;
> + Â Â Â Â Â Â Â fprintf(stderr, "%s%02X",
> + Â Â Â Â Â Â Â Â Â Â Â ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
> + Â Â Â Â Â Â Â Â Â Â Â data[i]);
> + Â Â Â }
> + Â Â Â fprintf(stderr, "\n");
> +#endif
> +}
> +
> +
> +static inline void debug_desc(struct desc *desc)
> +{
> +#if DEBUG_DESC
> + Â Â Â fprintf(stderr, "%07X: %X %3X %3X %07X %2X < %2X %4X %X"
> + Â Â Â Â Â Â Â " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
> + Â Â Â Â Â Â Â (u32)desc, (u32)desc->next, desc->buf_len, desc->pkt_len,
> + Â Â Â Â Â Â Â (u32)desc->data, desc->dest_id, desc->src_id, desc->flags,
> + Â Â Â Â Â Â Â desc->qos, desc->padlen, desc->vlan_tci,
> + Â Â Â Â Â Â Â desc->dst_mac[0], desc->dst_mac[1], desc->dst_mac[2],
> + Â Â Â Â Â Â Â desc->dst_mac[3], desc->dst_mac[4], desc->dst_mac[5],
> + Â Â Â Â Â Â Â desc->src_mac[0], desc->src_mac[1], desc->src_mac[2],
> + Â Â Â Â Â Â Â desc->src_mac[3], desc->src_mac[4], desc->src_mac[5]);
> +#endif
> +}
> +
> +static inline int queue_get_desc(unsigned int queue, struct port *port,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âint is_tx)
> +{
> + Â Â Â u32 addr, n;
> + Â Â Â struct desc *tab;
> +
> + Â Â Â if (!(addr = qmgr_get_entry(queue)))
> + Â Â Â Â Â Â Â return -1;
> +
> + Â Â Â addr &= ~0x1F; /* mask out non-address bits */
> + Â Â Â tab = is_tx ? port->tx_desc_tab : port->rx_desc_tab;
> + Â Â Â n = (addr - (u32)tab) / sizeof(struct desc);
> + Â Â Â BUG_ON(n >= (is_tx ? TX_DESCS : RX_DESCS));
> + Â Â Â debug_desc((struct desc*)addr);
> + Â Â Â BUG_ON(tab[n].next);
> + Â Â Â return n;
> +}
> +
> +static inline void queue_put_desc(unsigned int queue, struct desc *desc)
> +{
> + Â Â Â debug_desc(desc);
> + Â Â Â BUG_ON(((u32)desc) & 0x1F);
> + Â Â Â qmgr_put_entry(queue, (u32)desc);
> + Â Â Â /* Don't check for queue overflow here, we've allocated sufficient
> + Â Â Â Â Âlength and queues >= 32 don't support this check anyway. */
> +}
> +
> +
> +static int ixp4xx_eth_poll(struct eth_device *dev)
> +{
> + Â Â Â struct port *port = dev->priv;
> + Â Â Â struct desc *desc;
> + Â Â Â u8 *buff;
> + Â Â Â int n, len;
> +
> +#if DEBUG_RX
> + Â Â Â fprintf(stderr, "%s%d: eth_poll\n", dev->dev.name, dev->dev.id);
> +#endif
> +
> + Â Â Â if ((n = queue_get_desc(RX_QUEUE(port), port, 0)) < 0) {
> +#if DEBUG_RX
> + Â Â Â Â Â Â Â fprintf(stderr, "%s%d: eth_poll = no packet received\n", dev->dev.name, dev->dev.id);
> +#endif
> + Â Â Â Â Â Â Â return 0;
> + Â Â Â }
> +
> + Â Â Â barrier();
> + Â Â Â desc = &port->rx_desc_tab[n];
> + Â Â Â buff = rx_buff(port, n);
> + Â Â Â len = desc->pkt_len;
> + Â Â Â /* process received frame */
> + Â Â Â memcpy((void *)NetRxPackets[0], buff, len);
> + Â Â Â debug_pkt(dev, "RX", desc->data, len);
> +
> + Â Â Â /* put the new buffer on RX-free queue */
> + Â Â Â desc->buf_len = MAX_MRU;
> + Â Â Â desc->pkt_len = 0;
> + Â Â Â queue_put_desc(RXFREE_QUEUE(port), desc);
> +
> + Â Â Â net_receive(NetRxPackets[0], len);
> +
> +#if DEBUG_RX
> + Â Â Â fprintf(stderr, "%s%d: eth_poll end\n", dev->dev.name, dev->dev.id);
> +#endif
> + Â Â Â return 0;
> +}
> +
> +
> +static int ixp4xx_eth_xmit(struct eth_device *dev, void *data, int len)
> +{
> + Â Â Â struct port *port = dev->priv;
> + Â Â Â int n;
> + Â Â Â struct desc *desc;
> +
> +#if DEBUG_TX
> + Â Â Â fprintf(stderr, "%s%d: eth_xmit\n", dev->dev.name, dev->dev.id);
> +#endif
> +
> + Â Â Â if (unlikely(len > 1500))
> + Â Â Â Â Â Â Â return -1;
> +
> + Â Â Â debug_pkt(dev, "TX", data, len);
> +
> + Â Â Â if ((n = queue_get_desc(TXDONE_QUEUE, port, 1)) < 0)
> + Â Â Â Â Â Â Â return -1; /* no free buffers */
> + Â Â Â desc = &port->tx_desc_tab[n];
> + Â Â Â desc->data = tx_buff(port, n);
> + Â Â Â desc->buf_len = desc->pkt_len = len;
> + Â Â Â memcpy(desc->data, data, len);
> +
> + Â Â Â /* NPE firmware pads short frames with zeros internally */
> + Â Â Â // wmb();
> + Â Â Â barrier();
> + Â Â Â queue_put_desc(TX_QUEUE(port), desc);
> +
> +#if DEBUG_TX
> + Â Â Â fprintf(stderr, "%s%d: eth_xmit end\n", dev->dev.name, dev->dev.id);
> +#endif
> + Â Â Â return 0;
> +}
> +
> +static void request_queues(struct port *port, struct eth_device *dev)
> +{
> + Â Â Â qmgr_request_queue(RXFREE_QUEUE(port), RX_DESCS, 0, 0, "%s:RX-free", dev->dev.name);
> + Â Â Â qmgr_request_queue(RX_QUEUE(port), RX_DESCS, 0, 0, "%s:RX", dev->dev.name);
> + Â Â Â qmgr_request_queue(TX_QUEUE(port), TX_DESCS, 0, 0, "%s:TX", dev->dev.name);
> +
> + Â Â Â /* Common TX-done queue handles buffers sent out by the NPEs */
> + Â Â Â qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â"%s:TX-done", dev->dev.name);
> +}
> +
> +static void release_queues(struct port *port)
> +{
> + Â Â Â qmgr_release_queue(RXFREE_QUEUE(port));
> + Â Â Â qmgr_release_queue(RX_QUEUE(port));
> + Â Â Â qmgr_release_queue(TX_QUEUE(port));
> + Â Â Â qmgr_release_queue(TXDONE_QUEUE);
> +}
> +
> +static void init_queues(struct port *port)
> +{
> + Â Â Â int i;
> +
> + Â Â Â memset(port->tx_desc_tab, 0, sizeof(port->tx_desc_tab)); /* descs */
> + Â Â Â memset(port->rx_desc_tab, 0, sizeof(port->rx_desc_tab));
> +
> + Â Â Â /* Setup RX buffers */
> + Â Â Â for (i = 0; i < RX_DESCS; i++) {
> + Â Â Â Â Â Â Â struct desc *desc = &port->rx_desc_tab[i];
> + Â Â Â Â Â Â Â desc->buf_len = MAX_MRU;
> + Â Â Â Â Â Â Â desc->data = rx_buff(port, i);
> + Â Â Â }
> +}
> +
> +static int ixp4xx_eth_open(struct eth_device *dev)
> +{
> + Â Â Â struct port *port = dev->priv;
> + Â Â Â struct npe *npe = port->npe;
> + Â Â Â struct msg msg;
> + Â Â Â int i, err;
> +
> +#if DEBUG_OPEN
> + Â Â Â fprintf(stderr, "%s%d: opening %p\n", dev->dev.name, dev->dev.id, dev);
> +#endif
> +
> + Â Â Â if (!npe_running(npe)) {
> + Â Â Â Â Â Â Â err = npe_load_firmware(npe);
> + Â Â Â Â Â Â Â if (err)
> + Â Â Â Â Â Â Â Â Â Â Â return err;
> +
> + Â Â Â Â Â Â Â if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
> + Â Â Â Â Â Â Â Â Â Â Â fprintf(stderr, "%s%d: %s not responding\n", dev->dev.name, dev->dev.id, npe->name);
> + Â Â Â Â Â Â Â Â Â Â Â return -EIO;
> + Â Â Â Â Â Â Â }
> + Â Â Â Â Â Â Â memcpy(port->firmware, msg.params + 2, 4);
> + Â Â Â }
> +
> + Â Â Â if (ixp4xx_adjust_link(dev))
> + Â Â Â Â Â Â Â return -ENOLINK;
> +
> + Â Â Â port->buff_tab = xmalloc((RX_DESCS + TX_DESCS) * MAX_MRU);
> +
> + Â Â Â memset(&msg, 0, sizeof(msg));
> + Â Â Â msg.cmd = NPE_VLAN_SETRXQOSENTRY;
> + Â Â Â msg.eth_id = LOGICAL_ID(port);
> + Â Â Â msg.params[3] = RX_QUEUE(port) | 0x80;
> + Â Â Â msg.params[4] = RX_QUEUE(port) >> 4; /* MSB of offset */
> + Â Â Â msg.params[5] = RX_QUEUE(port) << 4; /* LSB of offset */
> + Â Â Â for (i = 0; i < 8; i++) {
> + Â Â Â Â Â Â Â msg.params[1] = i;
> + Â Â Â Â Â Â Â if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ")) {
> + Â Â Â Â Â Â Â Â Â Â Â err = -EIO;
> + Â Â Â Â Â Â Â Â Â Â Â goto out;
> + Â Â Â Â Â Â Â }
> + Â Â Â }
> +
> + Â Â Â msg.cmd = NPE_EDB_SETPORTADDRESS;
> + Â Â Â msg.eth_id = PHYSICAL_ID(port);
> + Â Â Â memcpy(msg.params, port->pinfo->hwaddr, ETH_ALEN);
> + Â Â Â if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC")) {
> + Â Â Â Â Â Â Â err = -EIO;
> + Â Â Â Â Â Â Â goto out;
> + Â Â Â }
> +
> + Â Â Â memset(&msg, 0, sizeof(msg));
> + Â Â Â msg.cmd = NPE_FW_SETFIREWALLMODE;
> + Â Â Â msg.eth_id = LOGICAL_ID(port);
> + Â Â Â if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE")) {
> + Â Â Â Â Â Â Â err = -EIO;
> + Â Â Â Â Â Â Â goto out;
> + Â Â Â }
> +
> + Â Â Â request_queues(port, dev);
> + Â Â Â init_queues(port);
> +
> + Â Â Â for (i = 0; i < ETH_ALEN; i++)
> + Â Â Â Â Â Â Â __raw_writel(port->pinfo->hwaddr[i], &port->regs->hw_addr[i]);
> + Â Â Â __raw_writel(0x08, &port->regs->random_seed);
> + Â Â Â __raw_writel(0x12, &port->regs->partial_empty_threshold);
> + Â Â Â __raw_writel(0x30, &port->regs->partial_full_threshold);
> + Â Â Â __raw_writel(0x08, &port->regs->tx_start_bytes);
> + Â Â Â __raw_writel(0x15, &port->regs->tx_deferral);
> + Â Â Â __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
> + Â Â Â __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
> + Â Â Â __raw_writel(0x80, &port->regs->slot_time);
> + Â Â Â __raw_writel(0x01, &port->regs->int_clock_threshold);
> +
> + Â Â Â /* Populate queues with buffers, no failure after this point */
> + Â Â Â for (i = 0; i < TX_DESCS; i++)
> + Â Â Â Â Â Â Â queue_put_desc(TXDONE_QUEUE, &port->tx_desc_tab[i]);
> +
> + Â Â Â for (i = 0; i < RX_DESCS; i++)
> + Â Â Â Â Â Â Â queue_put_desc(RXFREE_QUEUE(port), &port->rx_desc_tab[i]);
> +
> + Â Â Â __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
> + Â Â Â __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
> + Â Â Â __raw_writel(0, &port->regs->rx_control[1]);
> + Â Â Â __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
> +
> +#if 0
> + Â Â Â qmgr_set_irq(RX_QUEUE(port), QUEUE_IRQ_SRC_NOT_EMPTY,
> + Â Â Â Â Â Â Â Â Â Âeth_rx_irq, dev);
> + Â Â Â qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
> + Â Â Â Â Â Â Â Â Â Âeth_txdone_irq, NULL);
> + Â Â Â qmgr_enable_irq(TXDONE_QUEUE);
> +#endif
> + Â Â Â memset(&msg, 0, sizeof(msg));
> +#if DEBUG_OPEN
> + Â Â Â fprintf(stderr, "%s%d opened\n", dev->dev.name, dev->dev.id);
> +#endif
> + Â Â Â return 0;
> +out:
> + Â Â Â free(port->buff_tab);
> + Â Â Â port->buff_tab = NULL;
> +#if DEBUG_OPEN
> + Â Â Â fprintf(stderr, "%s%d open failed (%i)\n", dev->dev.name, dev->dev.id, err);
> +#endif
> + Â Â Â return err;
> +}
> +
> +static void ixp4xx_eth_close(struct eth_device *dev)
> +{
> + Â Â Â struct port *port = dev->priv;
> + Â Â Â struct msg msg;
> + Â Â Â int buffs = RX_DESCS; /* allocated RX buffers */
> + Â Â Â int i;
> +
> +#if DEBUG_CLOSE
> + Â Â Â fprintf(stderr, "%s%d: closing\n", dev->dev.name, dev->dev.id);
> +#endif
> +#if 0
> + Â Â Â qmgr_disable_irq(RX_QUEUE(port));
> +#endif
> +
> + Â Â Â if (!port->buff_tab)
> + Â Â Â Â Â Â Â return; /* already closed */
> +
> + Â Â Â while (queue_get_desc(RXFREE_QUEUE(port), port, 0) >= 0)
> + Â Â Â Â Â Â Â buffs--;
> +
> + Â Â Â memset(&msg, 0, sizeof(msg));
> + Â Â Â msg.cmd = NPE_SETLOOPBACK_MODE;
> + Â Â Â msg.eth_id = LOGICAL_ID(port);
> + Â Â Â msg.params[1] = 1;
> + Â Â Â if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
> + Â Â Â Â Â Â Â fprintf(stderr, "%s%d: unable to enable loopback\n", dev->dev.name, dev->dev.id);
> +
> +#if DEBUG_CLOSE
> + Â Â Â fprintf(stderr, "%s%d: draining RX queue\n", dev->dev.name, dev->dev.id);
> +#endif
> + Â Â Â i = 0;
> + Â Â Â do { /* drain RX buffers */
> + Â Â Â Â Â Â Â while (queue_get_desc(RX_QUEUE(port), port, 0) >= 0)
> + Â Â Â Â Â Â Â Â Â Â Â buffs--;
> + Â Â Â Â Â Â Â if (!buffs)
> + Â Â Â Â Â Â Â Â Â Â Â break;
> + Â Â Â Â Â Â Â if (qmgr_stat_full(TXDONE_QUEUE) && !(i % 10)) {
> + Â Â Â Â Â Â Â Â Â Â Â /* we have to inject some packet */
> + Â Â Â Â Â Â Â Â Â Â Â struct desc *desc;
> + Â Â Â Â Â Â Â Â Â Â Â int n = queue_get_desc(TXDONE_QUEUE, port, 1);
> + Â Â Â Â Â Â Â Â Â Â Â BUG_ON(n < 0);
> + Â Â Â Â Â Â Â Â Â Â Â desc = &port->tx_desc_tab[n];
> + Â Â Â Â Â Â Â Â Â Â Â desc->buf_len = desc->pkt_len = 1;
> + Â Â Â Â Â Â Â Â Â Â Â //wmb();
> + Â Â Â Â Â Â Â Â Â Â Â barrier();
> + Â Â Â Â Â Â Â Â Â Â Â queue_put_desc(TX_QUEUE(port), desc);
> + Â Â Â Â Â Â Â }
> + Â Â Â Â Â Â Â udelay(1);
> + Â Â Â } while (++i < MAX_CLOSE_WAIT);
> +
> + Â Â Â if (buffs)
> + Â Â Â Â Â Â Â fprintf(stderr, "%s%d: unable to drain RX queue, %i buffer(s) left in NPE\n",
> + Â Â Â Â Â Â Â Â Â Â Â dev->dev.name, dev->dev.id, buffs);
> +#if DEBUG_CLOSE
> + Â Â Â if (!buffs)
> + Â Â Â Â Â Â Â fprintf(stderr, "%s%d: draining RX queue took %i cycles\n", dev->dev.name, dev->dev.id, i);
> +#endif
> +
> + Â Â Â buffs = TX_DESCS;
> + Â Â Â while (queue_get_desc(TX_QUEUE(port), port, 1) >= 0)
> + Â Â Â Â Â Â Â buffs--; /* cancel TX */
> +
> + Â Â Â i = 0;
> + Â Â Â do {
> + Â Â Â Â Â Â Â while (queue_get_desc(TXDONE_QUEUE, port, 1) >= 0)
> + Â Â Â Â Â Â Â Â Â Â Â buffs--;
> + Â Â Â Â Â Â Â if (!buffs)
> + Â Â Â Â Â Â Â Â Â Â Â break;
> + Â Â Â } while (++i < MAX_CLOSE_WAIT);
> +
> + Â Â Â if (buffs)
> + Â Â Â Â Â Â Â fprintf(stderr, "%s%d: unable to drain TX queue, %i buffer(s) left in NPE\n",
> + Â Â Â Â Â Â Â Â Â Â Â dev->dev.name, dev->dev.id, buffs);
> +#if DEBUG_CLOSE
> + Â Â Â if (!buffs)
> + Â Â Â Â Â Â Â fprintf(stderr, "%s%d: draining TX queues took %i cycles\n", dev->dev.name, dev->dev.id, i);
> +#endif
> +
> + Â Â Â msg.params[1] = 0;
> + Â Â Â if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
> + Â Â Â Â Â Â Â fprintf(stderr, "%s%d: unable to disable loopback\n", dev->dev.name, dev->dev.id);
> +
> +#if 0
> + Â Â Â qmgr_disable_irq(TXDONE_QUEUE);
> +#endif
> + Â Â Â release_queues(port);
> + Â Â Â free(port->buff_tab);
> + Â Â Â port->buff_tab = NULL;
> +#if DEBUG_CLOSE
> + Â Â Â fprintf(stderr, "%s%d: closed\n", dev->dev.name, dev->dev.id);
> +#endif
> +}
> +
> +static int ixp4xx_eth_get_hwaddr(struct eth_device *eth, unsigned char *addr)
> +{
> + Â Â Â struct port *port = eth->priv;
> + Â Â Â memcpy(addr, port->pinfo->hwaddr, 6);
> + Â Â Â return 0;
> +}
> +
> +static int ixp4xx_eth_set_hwaddr(struct eth_device *eth, unsigned char *addr)
> +{
> + Â Â Â struct port *port = eth->priv;
> + Â Â Â memcpy(port->pinfo->hwaddr, addr, 6);
> + Â Â Â return 0;
> +}
> +
> +static int ixp4xx_eth_init(struct eth_device *eth)
> +{
> + Â Â Â struct port *port = eth->priv;
> +
> + Â Â Â __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
> + Â Â Â Â Â Â Â Â Â Â&port->regs->core_control);
> + Â Â Â udelay(50);
> + Â Â Â __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
> + Â Â Â udelay(50);
> +
> + Â Â Â miidev_restart_aneg(&port->miidev);
> + Â Â Â return 0;
> +}
> +
> +static int ixp4xx_eth_probe(struct device_d *dev)
> +{
> + Â Â Â struct npe *npe;
> + Â Â Â struct port *port;
> + Â Â Â struct eth_plat_info *pinfo = dev->platform_data;
> +
> + Â Â Â if (!pinfo) {
> + Â Â Â Â Â Â Â fprintf(stderr, "ixp4xx_eth: no platform information\n");
> + Â Â Â Â Â Â Â return -ENODEV;
> + Â Â Â }
> +
> + Â Â Â if (!(npe = npe_request(pinfo->npe))) {
> + Â Â Â Â Â Â Â fprintf(stderr, "ixp4xx_eth: unable to acquire NPE\n");
> + Â Â Â Â Â Â Â return -ENODEV;
> + Â Â Â }
> +
> + Â Â Â port = memalign(0x20, sizeof(*port));
> + Â Â Â memset(port, 0, sizeof(*port));
> +
> + Â Â Â port->regs = pinfo->regs;
> + Â Â Â port->npe = npe;
> + Â Â Â port->pinfo = pinfo;
> + Â Â Â port->eth.dev.id = -1;
> + Â Â Â port->eth.priv = port;
> + Â Â Â port->eth.init = ixp4xx_eth_init;
> + Â Â Â port->eth.open = ixp4xx_eth_open;
> + Â Â Â port->eth.halt = ixp4xx_eth_close;
> + Â Â Â port->eth.send = ixp4xx_eth_xmit;
> + Â Â Â port->eth.recv = ixp4xx_eth_poll;
> + Â Â Â port->eth.get_ethaddr = ixp4xx_eth_get_hwaddr;
> + Â Â Â port->eth.set_ethaddr = ixp4xx_eth_set_hwaddr;
> +
> + Â Â Â port->miidev.dev.id = -1;
> + Â Â Â port->miidev.read = ixp4xx_mdio_read;
> + Â Â Â port->miidev.write = ixp4xx_mdio_write;
> + Â Â Â port->miidev.address = pinfo->phy;
> + Â Â Â port->miidev.edev = &port->eth;
> + Â Â Â mii_register(&port->miidev);
> + Â Â Â eth_register(&port->eth);
> + Â Â Â return 0;
> +}
> +
> +static struct driver_d ixp4xx_eth_driver = {
> + Â Â Â .name Â= "ixp4xx_eth",
> + Â Â Â .probe = ixp4xx_eth_probe,
> +};
> +
> +static int __init ixp4xx_eth_module_init(void)
> +{
> + Â Â Â if (cpu_is_ixp43x()) {
> + Â Â Â Â Â Â Â /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */
> + Â Â Â Â Â Â Â if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEC_ETH))
> + Â Â Â Â Â Â Â Â Â Â Â return -ENOSYS;
> + Â Â Â Â Â Â Â mdio_regs = (struct eth_regs *)IXP4XX_EthC_BASE;
> + Â Â Â } else {
> + Â Â Â Â Â Â Â /* All MII PHY accesses use NPE-B Ethernet registers */
> + Â Â Â Â Â Â Â if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
> + Â Â Â Â Â Â Â Â Â Â Â return -ENOSYS;
> + Â Â Â Â Â Â Â mdio_regs = (struct eth_regs *)IXP4XX_EthB_BASE;
> + Â Â Â }
> +
> + Â Â Â __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
> +
> + Â Â Â register_driver(&ixp4xx_eth_driver);
> + Â Â Â return 0;
> +}
> +
> +device_initcall(ixp4xx_eth_module_init);
> diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
> index 290619f..0f25ceb 100644
> --- a/drivers/serial/serial_ns16550.c
> +++ b/drivers/serial/serial_ns16550.c
> @@ -102,7 +102,11 @@ static void ns16550_serial_init_port(struct console_device *cdev)
> Â Â Â Âbaud_divisor = ns16550_calc_divisor(cdev, CONFIG_BAUDRATE);
>
> Â Â Â Â/* initializing the device for the first time */
> +#ifdef CONFIG_ARCH_IXP4XX
> + Â Â Â plat->reg_write(IER_UUE, base, ier); /* Enable UART operation */
> +#else
> Â Â Â Âplat->reg_write(0x00, base, ier);
> +#endif
> Â#ifdef CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS
> Â Â Â Âplat->reg_write(0x07, base, mdr1); Â Â Â/* Disable */
> Â#endif
> @@ -181,7 +185,11 @@ static int ns16550_setbaudrate(struct console_device *cdev, int baud_rate)
> Â Â Â Â Â Âcdev->dev->platform_data;
> Â Â Â Âunsigned long base = cdev->dev->map_base;
> Â Â Â Âunsigned int baud_divisor = ns16550_calc_divisor(cdev, baud_rate);
> +#ifdef CONFIG_ARCH_IXP4XX
> + Â Â Â plat->reg_write(IER_UUE, base, ier); /* Enable UART operation */
> +#else
> Â Â Â Âplat->reg_write(0x00, base, ier);
> +#endif
> Â Â Â Âplat->reg_write(LCR_BKSE, base, lcr);
> Â Â Â Âplat->reg_write(baud_divisor & 0xff, base, dll);
> Â Â Â Âplat->reg_write((baud_divisor >> 8) & 0xff, base, dlm);
> diff --git a/drivers/serial/serial_ns16550.h b/drivers/serial/serial_ns16550.h
> index eb2fd10..ba20a6f 100644
> --- a/drivers/serial/serial_ns16550.h
> +++ b/drivers/serial/serial_ns16550.h
> @@ -50,6 +50,8 @@
> Â#define dll      Ârbr
> Â#define dlm      Âier
>
> +#define IER_UUE Â Â Â Â Â Â Â Â0x40 Â Â/* UART Unit Enable (XScale) */
> +
> Â#define FCR_FIFO_EN Â Â 0x01 Â /* Fifo enable */
> Â#define FCR_RXSR Â Â Â Â0x02 Â /* Receiver soft reset */
> Â#define FCR_TXSR Â Â Â Â0x04 Â /* Transmitter soft reset */
>
> _______________________________________________
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> barebox@xxxxxxxxxxxxxxxxxxx
> http://lists.infradead.org/mailman/listinfo/barebox
>

thanks,

marek

-- 
as simple and primitive as possible
-------------------------------------------------
Marek Belisko - OPEN-NANDRA
Freelance Developer

Ruska Nova Ves 219 | Presov, 08005 Slovak Republic
Tel: +421 915 052 184
skype: marekwhite
icq: 290551086
web: http://open-nandra.com

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