Hi Fredrik, > > I wonder if FS=1 hardwired also means the Underflow exception cannot > > happen. As the corresponding Cause and Enable bits cannot be set together > > or an FPE exception will happen right away, and the Unimplemented > > Operation exception is uncoditional so we need to leave it out, can you > > please also try these masks in turns: > > > > " li %1,0x0001f07c\n" > > > > and: > > > > " li %1,0x00000f80\n" > > > > This will reveal if any of the Cause, Enable or Flag bits are hardwired. > > The result is: > > FCSR 0x0001f07c old: 01000001, new: 0101c079 > FCSR 0x00000f80 old: 01000001, new: 01000001 This looks unusual and inconsistent in that only V, Z and O Cause bits appear settable, these and also I Flag bits do and no Enable bits do. Given Jürgen's observations in the discussion you referred to below I would expect the I Flag bit not to be settable either; perhaps it's a hardware erratum. > I was looking for information on GCC for R5900 and found > > https://gcc.gnu.org/ml/gcc-patches/2013-01/msg00658.html > > where you and Jürgen Urban discuss this topic. Jürgen cites some FPU details > from the Emotion Engine core user's manual that is very helpful, in addition > to mentioning TX79 differences. Thanks for the reference, I did remember I had the discussion, but didn't recall the details, although I had a vague recollection about instruction encoding differences. Given the situation I think we'll have to stick with full FPU emulation for regular MIPS/Linux user programs, and then possibly have an ELF ABI flag of sorts to mark software requesting running in the R5900 hard-float mode (which obviously won't be able to use standard `libm', etc.); we can think of doing it in a way to keep binary compatibility with exiting PS2 software, should this be a concern. Tasks run in the R5900 hard-float mode would then have our FPU emulator strapped for pass-through operation, i.e. the CpU exception and context switching would work normally, however any FPE exception, given the findings above about FCSR possibly including Unimplemented Operation only, would just throw SIGFPE, letting the userland handle it if desired. You'd need a new `si_code' of course for Unimplemented Operation; or maybe not even that, because as vague as Jürgen's notes are they seem to suggest the R5900 may not actually trap with FPE ever. This also means you only want FPU_CSR_CONDX in `c->fpu_msk31' (for the full FPU emulation) as with an ordinary MIPS III processor. NB, I think the issue with RDHWR emulation to access CP0.UserLocal mentioned in the discussion referred will have to be addressed with the initial submission as well. Maciej
