Hi Maciej,
> If you don't have documentation, but you have the hardware at hand, then
> you'll best check it yourself by writing a small user program that writes
> to CP1.FCSR and checks which bits stick (of course you need to leave the
> exception cause/mask bits alone for this check or you'll get SIGFPE sent
> instead).
Did you have something like this in mind? It prints 01000001 so the bits
above FS does not seem to stick.
uint32_t fcr31;
asm volatile (" cfc1 $t0,$31\n"
" lui $t1,0xfe00\n"
" or $t0,$t1,$t0\n"
" ctc1 $t0,$31\n"
" nop\n"
" cfc1 $t0,$31\n"
" nop\n"
" move %0,$t0\n" : "=r" (fcr31));
printf("fcr31 %08" PRIx32 "\n", fcr31);
The "TX System RISC TX79 Core Architecture" manual says that both data and
instruction caches are 32 kB, but other sources seem to contradict this with
8 kB for data and 16 kB for instructions. So R5900 and C790 seem to be very
similar but not identical which could bring various surprises. Here is
another source:
https://www.linux-mips.org/wiki/PS2
Fredrik
