Hi Fredrik,
> > If you don't have documentation, but you have the hardware at hand, then
> > you'll best check it yourself by writing a small user program that writes
> > to CP1.FCSR and checks which bits stick (of course you need to leave the
> > exception cause/mask bits alone for this check or you'll get SIGFPE sent
> > instead).
>
> Did you have something like this in mind? It prints 01000001 so the bits
> above FS does not seem to stick.
>
> uint32_t fcr31;
> asm volatile (" cfc1 $t0,$31\n"
> " lui $t1,0xfe00\n"
> " or $t0,$t1,$t0\n"
> " ctc1 $t0,$31\n"
> " nop\n"
> " cfc1 $t0,$31\n"
> " nop\n"
> " move %0,$t0\n" : "=r" (fcr31));
NB you're missing clobbers for $t0 and $t1 here, which may cause odd
results (since you've named these registers explicitly rather than letting
GCC choose them via constraints).
> printf("fcr31 %08" PRIx32 "\n", fcr31);
Yes, this is roughly what I had in mind, although you could have used an
upper mask of 0xfffc to double-check the other bits. Thanks for doing
this check.
I find it odd to see the FS bit set though, it shouldn't be as neither
the kernel nor glibc startup sets it -- is it hardwired by any chance?
If so, then it has to be reflected both in `->fpu_msk31' and in
`->fpu_csr31', in particular for the `nofpu' mode to closely follow
hardware (but also for some obscure corner cases where CTC1 is emulated
even in the regular FPU operation mode).
Can you please try flipping the bits instead then, e.g.:
uint32_t fcsr0, fcsr1;
asm volatile (" cfc1 %0,$31\n"
" lui %1,0xfffc\n"
" xor %1,%0\n"
" ctc1 %1,$31\n"
" nop\n"
" cfc1 %1,$31\n"
" ctc1 %0,$31\n"
: "=r" (fcsr0), "=r" (fcsr1));
printf("FCSR old: %08" PRIx32 ", new: %08" PRIx32 "\n", fcsr0, fcsr1);
[NB there are no pipeline hazards in accessing the FCRs according to
Section 10.2.4 "Accessing the FP Control and Implementation/Revision
Registers" of the TX79 manual, however I've left the NOP in place as it
won't hurt and may be needed by other hardware.]
You then effectively need to set:
->fpu_csr31 = (old & new) & 0xfffc0000;
->fpu_msk31 = (old ^ ~new) & 0xfffc0000;
however see examples throughout arch/mips/kernel/cpu-probe.c for how to
use macros rather than magic numbers to express bits on the RHS. We avoid
run-time probing for FCSR bits to avoid unpredictable behaviour some
hardware can show.
> The "TX System RISC TX79 Core Architecture" manual says that both data and
> instruction caches are 32 kB, but other sources seem to contradict this with
> 8 kB for data and 16 kB for instructions. So R5900 and C790 seem to be very
> similar but not identical which could bring various surprises. Here is
> another source:
>
> https://www.linux-mips.org/wiki/PS2
Cache sizes may well have been an RTL option and the base architecture
the same. Of course it would help if we had accurate documentation, but
as often we need to live with whatever we have available.
Maciej
