Hi Maciej,
> > Can you please try flipping the bits instead then, e.g.:
> >
> > uint32_t fcsr0, fcsr1;
> > asm volatile (" cfc1 %0,$31\n"
> > " lui %1,0xfffc\n"
>
> Actually can you please substitute:
>
> " li %1,0xfffc0003\n"
>
> here, so that we know how RM behaves?
Sure. I get "FCSR old: 01000001, new: 01800001" with the R5900.
> Again, it is odd to see it set to 1 (towards zero) by default and if it
> is hardwired, then `->fpu_csr31' and `->fpu_msk31' will have to be
> updated, AT_FPUCW exported and glibc adjusted.
Right. Quite a few details to resolve for the FPU then. Here is the
disassembly to double-check the compiled code:
004001c0 <main>:
4001c0: 3c1c0043 lui gp,0x43
4001c4: 27bdffe0 addiu sp,sp,-32
4001c8: 279c9470 addiu gp,gp,-27536
4001cc: afbf001c sw ra,28(sp)
4001d0: afbc0010 sw gp,16(sp)
4001d4: 4445f800 cfc1 a1,$31
4001d8: 3c06fffc lui a2,0xfffc
4001dc: 34c60003 ori a2,a2,0x3
4001e0: 00c53026 xor a2,a2,a1
4001e4: 44c6f800 ctc1 a2,$31
4001e8: 00000000 nop
4001ec: 4446f800 cfc1 a2,$31
4001f0: 44c5f800 ctc1 a1,$31
4001f4: 8f9980f4 lw t9,-32524(gp)
4001f8: 3c040041 lui a0,0x41
4001fc: 04110094 bal 400450 <__GI_printf>
400200: 2484f720 addiu a0,a0,-2272
400204: 8fbf001c lw ra,28(sp)
400208: 00001021 move v0,zero
40020c: 03e00008 jr ra
400210: 27bd0020 addiu sp,sp,32
Fredrik
