On Fri, Mar 31, 2017 at 11:02:33AM +0200, Thomas Gleixner wrote: > On Thu, 30 Mar 2017, Paul Burton wrote: > > > This series introduces support for IPI IRQ domains to the CPU interrupt > > controller driver, allowing IPIs to function in the same way as those > > provided by the MIPS GIC as far as platform/board code is concerned. > > > > Doing this allows us to avoid duplicating code across platforms, avoid > > having to handle cases where IPI domains are or aren't in use depending > > upon the interrupt controller, and strengthen a sanity check for cases > > where IPI IRQ domains are supported. > > For the irqchip parts: > > Acked-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx> > > Ralf, feel free to route the whole lot through your MIPS tree. Done. Nice cleanup, Paul. Ralf
