On 03/30/2017 15:06, Paul Burton wrote: > This series introduces support for IPI IRQ domains to the CPU interrupt > controller driver, allowing IPIs to function in the same way as those > provided by the MIPS GIC as far as platform/board code is concerned. > > Doing this allows us to avoid duplicating code across platforms, avoid > having to handle cases where IPI domains are or aren't in use depending > upon the interrupt controller, and strengthen a sanity check for cases > where IPI IRQ domains are supported. > > Applies atop v4.11-rc4. > > > Paul Burton (5): > irqchip: mips-cpu: Replace magic 0x100 with IE_SW0 > irqchip: mips-cpu: Prepare for non-legacy IRQ domains > irqchip: mips-cpu: Introduce IPI IRQ domain support > MIPS: smp-mt: Use CPU interrupt controller IPI IRQ domain support > MIPS: Stengthen IPI IRQ domain sanity check > > arch/mips/kernel/smp-mt.c | 49 ++------------ > arch/mips/kernel/smp.c | 20 +++--- > arch/mips/lantiq/irq.c | 52 -------------- > arch/mips/mti-malta/malta-int.c | 83 ++--------------------- > drivers/irqchip/Kconfig | 2 + > drivers/irqchip/irq-mips-cpu.c | 146 +++++++++++++++++++++++++++++++++++----- > 6 files changed, 151 insertions(+), 201 deletions(-) Out of curiosity, "legacy" systems like SGI IP27 (in-tree) and IP30 (external) support SMP and the IRQ handling is fairly old for IP27 (IP30 borrows IP27's logic). Could these systems benefit from using IPI domains? If so, is there any kind of crash-course or dummies guide to switching from plain irq_chip to IPI domains? Note, both systems have somewhat unique interrupt controllers built into their system ASICs, but actual IRQ dispatch happens from the CPU interrupt pins. Thanks!, -- Joshua Kinard Gentoo/MIPS kumba@xxxxxxxxxx 6144R/F5C6C943 2015-04-27 177C 1972 1FB8 F254 BAD0 3E72 5C63 F4E3 F5C6 C943 "The past tempts us, the present confuses us, the future frightens us. And our lives slip away, moment by moment, lost in that vast, terrible in-between." --Emperor Turhan, Centauri Republic
