This series introduces support for IPI IRQ domains to the CPU interrupt controller driver, allowing IPIs to function in the same way as those provided by the MIPS GIC as far as platform/board code is concerned. Doing this allows us to avoid duplicating code across platforms, avoid having to handle cases where IPI domains are or aren't in use depending upon the interrupt controller, and strengthen a sanity check for cases where IPI IRQ domains are supported. Applies atop v4.11-rc4. Paul Burton (5): irqchip: mips-cpu: Replace magic 0x100 with IE_SW0 irqchip: mips-cpu: Prepare for non-legacy IRQ domains irqchip: mips-cpu: Introduce IPI IRQ domain support MIPS: smp-mt: Use CPU interrupt controller IPI IRQ domain support MIPS: Stengthen IPI IRQ domain sanity check arch/mips/kernel/smp-mt.c | 49 ++------------ arch/mips/kernel/smp.c | 20 +++--- arch/mips/lantiq/irq.c | 52 -------------- arch/mips/mti-malta/malta-int.c | 83 ++--------------------- drivers/irqchip/Kconfig | 2 + drivers/irqchip/irq-mips-cpu.c | 146 +++++++++++++++++++++++++++++++++++----- 6 files changed, 151 insertions(+), 201 deletions(-) -- 2.12.1
