On Thu, Oct 06, 2016 at 08:56:50PM +0100, Maciej W. Rozycki wrote: > On Thu, 6 Oct 2016, James Hogan wrote: > > > > ISTR a while ago we had a rather lengthy discussion as to how to detect > > > the presence of the upper 32 bits without triggering undefined behaviour > > > implied by 64-bit CP0 accesses to 32-bit CP0 registers. As I believe we > > > set EBase ourselves I think we are able to make the necessary checks and > > > have an accurate condition here, still remembering however that it may go > > > back as far as MIPSr3. > > > > We only set ebase under certain circumstances, otherwise leaving it as > > already set. > > How can we install a handler then when we don't know what the upper 32 > bits of EBase are? Right now its assumed the default upper 32 bits are sign extension of bit 31 in that case (i.e. thats what upper 32bits are clobbered to). I think the only case where that might not be true would be where WG is implemented and the bootloader has changed them to e.g. somewhere in XKPhys, and then cleared WG. We could catch that most of the time by detecting changed bits 31:30 (as I think you suggested before), but it still isn't watertight (e.g. xkphys+0x80000000), so if in doubt we should probably be sure to allocate our own exception vector instead of guessing at the boot one. What a mess :-(. Cheers James
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