On Thu, 6 Oct 2016, James Hogan wrote: > > ISTR a while ago we had a rather lengthy discussion as to how to detect > > the presence of the upper 32 bits without triggering undefined behaviour > > implied by 64-bit CP0 accesses to 32-bit CP0 registers. As I believe we > > set EBase ourselves I think we are able to make the necessary checks and > > have an accurate condition here, still remembering however that it may go > > back as far as MIPSr3. > > We only set ebase under certain circumstances, otherwise leaving it as > already set. How can we install a handler then when we don't know what the upper 32 bits of EBase are? Maciej
