Hi James, > > This does look wrong to me, as I noted above EBase is 64-bit with MIPS64 > > processors as from architecture revision 3.50. Also I don't think we want > > MIPS64 PRA (I'm looking at r5 and r6) seems to allow for write-gate not > to be implemented, in which case the register is only 32-bits. Indeed, but we need to be prepared to handle the width of 64 bits and `cpu_has_mips64r6' does not seem to me to be the right condition. ISTR a while ago we had a rather lengthy discussion as to how to detect the presence of the upper 32 bits without triggering undefined behaviour implied by 64-bit CP0 accesses to 32-bit CP0 registers. As I believe we set EBase ourselves I think we are able to make the necessary checks and have an accurate condition here, still remembering however that it may go back as far as MIPSr3. Maciej
